Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.

Abstract: An active analog filter (700, 1000) having a MOS capacitor device (730, 1030) with improved linearity is proposed. In an exemplary embodiment, dc bias voltage sources (755, 745) alter the capacitance of MOS varactors (740, 750) connected in anti parallel so that the total capacitance of the MOS capacitor device remains constant or within a range over the voltage range of the filter and the filter linearity is set. In a further exemplary embodiment the output stage (1070) of the operational amplifier circuit (1020) of the active analog filter (1000) is modified so that the dc bias voltage is provided by resistors (1055, 1045) connected to a current source (1060) already existing in the filter. Thus the linearity is set and the die area is significantly reduced.

Abstract: A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.

Abstract: A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

Abstract: A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

Abstract: An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.

Abstract: A class AB amplifier with resistive level-shifting circuitry is described. In one exemplary design, the class AB amplifier includes an input stage, a resistive level-shifting stage, a class AB output stage, and a bias circuit. The input stage receives an input signal and provides a first drive signal. The resistive level-shifting stage receives the first drive signal and provides a second drive signal. The output stage receives the first and second drive signals and provides an output signal. The bias circuit generates a bias voltage for the resistive level-shifting stage to obtain a desired quiescent current for the output stage. In one exemplary design, the resistive level-shifting stage includes a transistor and a resistor. The transistor receives the bias voltage and provides the second drive signal. The resistor is coupled to the transistor and provides a voltage drop between the first and second drive signals.

Abstract: Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.

Abstract: An apparatus includes first and second filters and a bandwidth control circuit. The first filter operates as part of a first oscillator in a first mode and filters a first input signal and provides a first output signal in a second mode. The second filter operates as part of a second oscillator in the first mode and filters a second input signal and provides a second output signal in the second mode. The bandwidth control circuit adjusts the bandwidth of the first and second filters in the first mode, e.g., adjusts the oscillation frequency of each oscillator to obtain a target bandwidth for an associated filter. The apparatus may further include first and second gain control circuits. Each gain control circuit may vary the amplitude of an oscillator signal from an associated oscillator and/or set a gain of an associated filter in the first mode.

Abstract: A communication device includes a transmitter and a receiver. The receiver mixes a local oscillator (LO) signal with the received signal to downconvert the received signal to an intermediate frequency (IF). The LO path that feeds the LO signal to the downconverting mixer is controlled based on the transmit power of the transmitter. For high transmit power, the drive of the LO path is increased, thereby increasing the signal-to-noise ratio of the LO signal input into the mixer. For low transmit power levels, the drive to the LO path is decreased, reducing power consumption in the communication device. In this way, receiver path noise due to mixing of the LO phase noise with the self-generated transmitter signal is selectively controlled while incurring lower power consumption penalty. The communication device may be an access terminal configured for communication with a cellular radio network.

Abstract: A circuit controls an oscillation amplitude of a crystal oscillator including a crystal resonator, a current source supplying a bias current, and an output transistor coupled to the crystal resonator and the current source. The circuit includes a peak detector for detecting a peak voltage of an output signal of the crystal oscillator, and a controller coupled to the peak detector and to the current source for controlling the current source in accordance with a difference between the peak voltage and a target voltage, the target voltage being set to be substantially equal to 2Vth, where Vth is a threshold voltage of the output transistor. A frequency control circuit controls a first switched-capacitor array and a second switched-capacitor array coupled to the crystal resonator, and alternately switches a unit capacitor in the first switched-capacitor array and a unit capacitor in the second switched-capacitor array based on a frequency control signal.

Abstract: A system and method are disclosed for equalizing a read signal from a data storage media is disclosed. An analog output signal is equalized by reading the data storage media using an analog equalization filter. The analog output of the analog equalization filter is converted to a raw digital output signal. The raw digital output signal is processed to detect and correct an error in the raw digital output signal. The error is detected and an adjustment is made to the boost of the analog equalization filter according to the error detected.

Abstract: An initial phase control for an oscillator such as a differential ring voltage-controlled oscillator is disclosed. The initial phase control generally comprises a current source circuit coupled to a first node of the delay cell and a current provider. The current source circuit and current provider are preferably selectively and synchronously in an on or off state such that when the current source circuit and current provider are in an on state, the current source circuit draws a current through the first node of the delay cell and the current provider provides current through a second node of the delay cell. A method for controlling a delay cell and an initial phase control for a differential ring oscillator having a plurality of delay cells in a ring configuration are also disclosed.

Abstract: A system and method for reduced metastability errors in an analog-to-digital converter (“ADC”) are disclosed. The ADC comprises comparators configured to output a thermometer code and a thermometer-to-binary encoder for converting the thermometer code to a digital output.

Abstract: An improved Viterbi detector for use in a partial-response maximum-likelihood (PRML) channel. The present invention reduces the amount of hardware necessary in the conventional digital implementation, as well as increasing the speed of the system, by utilizing analog circuits. Whereas prior art analog implementations use more complex hardware and less efficient algorithms, the present invention utilizes easily realizable circuitry to perform a more efficient algorithm. A sampled data Viterbi detector compares a sampled analog input signal with two threshold signals. The binary outputs of the comparing means are then provided to a survival sequence register, as well as being used to formulate new threshold signals for the subsequent input sample. The hardware implements Ferguson's method for calculating sequence metrics by representing the accumulated metric difference as two threshold signals. Probability based decisions are then performed in analog comparators.

Abstract: Analog-to-digital converter (ADC) output bits are partitioned in a way that simplifies the phase error calculations. The circuit architecture embeds the implementation of the phase error calculations in the analog-to digital-converter (ADC) to simplify the overall circuit implementation. Simplification of the phase error calculations allows a reduction in the complexity of the circuits needed to implement the phase-locked-loop (PLL) for recovering the sampling clock.

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm.

Abstract: A timing acquisition circuit using a phase locked loop with programmable damping for either Type A or Type B phase detectors is described. In the damping scheme for a Type A phase detector, a resistance (R1) is simulated by adding an equivalent voltage Veff to the capacitor voltage. The equivalent voltage Veff is generated internally, so that programmable damping is made possible. In Type B phase detectors, a variable gain amplifier is used to control the effective resistance (R1) of the loop filter.

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm.