Abstract: A semiconductor device may be provided. The semiconductor device may include a first guard ring disposed in a first region, and a second guard ring disposed in a second region. The semiconductor device may include a first metal line and a second metal line respectively disposed over the first guard ring and the second guard ring, and respectively coupled to the first guard ring and the second guard ring. The semiconductor device may include a gate pattern coupled to the first metal line or the second metal line, wherein the first metal line and the second metal line are configured to respectively receive a first voltage and a second voltage. The second voltage may have a different potential from the first voltage.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first guard ring disposed in a first region, and a second guard ring disposed in a second region. The semiconductor device may include a first metal line and a second metal line respectively disposed over the first guard ring and the second guard ring, and respectively coupled to the first guard ring and the second guard ring. The semiconductor device may include a gate pattern coupled to the first metal line or the second metal line, wherein the first metal line and the second metal line are configured to respectively receive a first voltage and a second voltage. The second voltage may have a different potential from the first voltage.

Abstract: A semiconductor device may include: a wiring layer formed over an interlayer dielectric layer; and one or more wiring characteristic control parts extended from the wiring layer into the interlayer dielectric layer. The bottom of the one or more wiring characteristic control parts may be positioned at a higher level than the bottom of the interlayer dielectric layer.