Abstract: An apparatus comprising a plurality of memory components each comprising a plurality of memory banks, a memory controller coupled to the memory components and configured to control and select a one of the plurality of memory components for a memory operation, a plurality of address/command buses coupled to the plurality of memory components and the memory controller comprising at least one shared address/command bus between at least some of the plurality of memory components, and a plurality of data buses coupled to the memory components and the memory controller comprising at least one data bus between at least some of the memory components, wherein the memory controller uses a memory interleaving and bank arbitration scheme in a time-division multiplexing (TDM) fashion to access the plurality of memory components and the memory banks.