Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.

Abstract: A fitness device includes a housing, a driving motor mounted on the housing, a fitness pull rope connected to the driving motor, and a control system connected to the driving motor. The control system comprises a main controller, a power module, a communication module, a driving circuit and a sampling module, the power module is electrically connected to the main controller and the communication module, the communication module is electrically connected to the main controller, the sampling module is electrically connected to the driving motor and the main controller, and the driving circuit is electrically connected to the power module, the main controller and the driving motor. The fitness pull rope is arranged on the driving motor functioning as a full driver, and the control system is used for controlling the pull force of the driving motor, thereby realizing smart fitness.

Abstract: Apparatuses, systems, and techniques to selectively use one or more neural network layers. In at least one embodiment, one or more neural network layers are selectively used based on, for example, one or more iteratively increasing neural network performance metrics.

Abstract: A semiconductor device includes a substrate, a semiconductor component and a heat dissipation component. The semiconductor component is disposed on the substrate. The heat dissipation component is disposed on the substrate and having a cavity, an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity.

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Abstract: A computer implemented method for certifying robustness of image classification in a neural network is provided. The method includes initializing a neural network model. The neural network model includes a problem space and a decision boundary. A processor receives a data set of images, image labels, and a perturbation schedule. Images are drawn from the data set in the problem space. A distance from the decision boundary is determined for the images in the problem space. A re-weighting value is applied to the images. A modified perturbation magnitude is applied to the images. A total loss function for the images in the problem space is determined using the re-weighting value. A confidence level of the classification of the images in the data set is evaluated for certifiable robustness.

Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

Abstract: Machine learning model training is provided. A model training result of a machine learning model is predicted utilizing a classification model based on a plurality of different combinations of input data set properties, settings of the machine learning model, and machine learning model training environment properties. Model training duration of the machine learning model is predicted utilizing a regression model based on those combinations that had a predicted successful model training result. Capacity unit hours is determined for each respective combination having the predicted successful model training result based on a corresponding predicted model training duration of the machine learning model. A particular combination of input data set properties, settings of the machine learning model, and machine learning model training environment properties that has minimum capacity unit hours is selected. The machine learning model is trained using the particular combination.

Abstract: Provided are a drive compensation method and system of a display panel and a display device. The drive compensation method includes: determining at least one of the impedance and capacitive reactance variation curve of a first signal line in a column direction and determining the charge rate variation curve of first pixel units in a row direction; determining the compensation coefficients for a respective pixel unit in the column direction and/or the row direction according to the impedance and capacitive reactance variation curve of the first signal line in the column direction and/or the charge rate variation curve of first pixel units in the row direction; and compensating the compensation coefficients for the respective pixel unit in the column direction and/or the row direction to the drive signal of the respective pixel unit to drive the respective pixel unit.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, an isolation layer, a gate stack structure, and a dielectric layer. The method includes partially removing the gate stack structure to form a first trench in the gate stack structure. The method includes forming an isolation structure in the first trench. The method includes removing the first gate stack and the second gate stack to form a first recess and a second recess in the dielectric layer. The method includes forming an n-type gate stack and a p-type gate stack in the first recess and the second recess respectively. The method includes forming a conductive line over the n-type gate stack, the p-type gate stack, and the isolation structure. The conductive line electrically connects the n-type gate stack to the p-type gate stack.

Abstract: The present application discloses a display panel, a display driving method for display panel, and a display apparatus. The display panel includes a plurality of rows of pixel circuits; a gate drive circuit configured to be switched between a first drive mode and a second drive mode, wherein the first drive mode comprises that the gate drive circuit provides gate signals to n rows of the pixel circuits simultaneously, and the second drive mode comprises that the gate drive circuit provides gate signals to m*n rows of the pixel circuits simultaneously, wherein n is a positive integer, and m is an integer greater than or equal to 2.

Abstract: The present application discloses a display panel, a display driving method for display panel, and a display apparatus. The display panel includes a plurality of rows of pixel circuits; a gate drive circuit configured to be switched between a first drive mode and a second drive mode, wherein the first drive mode comprises that the gate drive circuit provides gate signals to n rows of the pixel circuits simultaneously, and the second drive mode comprises that the gate drive circuit provides gate signals to m*n rows of the pixel circuits simultaneously, wherein n is a positive integer, and m is an integer greater than or equal to 2.

Abstract: Within many applications impulse radio based ultra-wideband (IR-UWB) transmission offers significant benefits for very short range high data rate communications when compared with existing standards and protocols. In many of these applications the main design goals are very low power consumption and very low complexity design for easy integration and cost reduction. Digitally programmable IR-UWB transmitters using an on-off keying modulation scheme on a 0.13 microns CMOS process operating on 1.2V supply and yielding power consumption as low as 0.9 mW at a 10 Mbps data rate with dynamic power control are enabled. The IR-UWB transmitters support new frequency hopping techniques providing more efficient spectrum usage and dynamic allocation of the spectrum when transmitting in highly congested frequency bands. Biphasic scrambling is also introduced for spectral line reduction.

Abstract: Within many applications impulse radio based ultra-wideband (IR-UWB) transmission offers significant benefits for very short range high data rate communications when compared with existing standards and protocols. In many of these applications the main design goals are very low power consumption and very low complexity design for easy integration and cost reduction. Digitally programmable IR-UWB transmitters using an on-off keying modulation scheme on a 0.13 microns CMOS process operating on 1.2V supply and yielding power consumption as low as 0.9 mW at a 10 Mbps data rate with dynamic power control are enabled. The IR-UWB transmitters support new frequency hopping techniques providing more efficient spectrum usage and dynamic allocation of the spectrum when transmitting in highly congested frequency bands. Biphasic scrambling is also introduced for spectral line reduction.

Abstract: Provided are a drive compensation method and system of a display panel and a display device. The drive compensation method includes: determining at least one of the impedance and capacitive reactance variation curve of a first signal line in a column direction and determining the charge rate variation curve of first pixel units in a row direction; determining the compensation coefficients for a respective pixel unit in the column direction and/or the row direction according to the impedance and capacitive reactance variation curve of the first signal line in the column direction and/or the charge rate variation curve of first pixel units in the row direction; and compensating the compensation coefficients for the respective pixel unit in the column direction and/or the row direction to the drive signal of the respective pixel unit to drive the respective pixel unit.

Abstract: Within many applications impulse radio based ultra-wideband (IR-UWB) transmission offers significant benefits for very short range high data rate communications when compared with existing standards and protocols. In many of these applications the main design goals are very low power consumption and very low complexity design for easy integration and cost reduction. Digitally programmable IR-UWB transmitters using an on-off keying modulation scheme on a 0.13 microns CMOS process operating on 1.2V supply and yielding power consumption as low as 0.9 mW at a 10 Mbps data rate with dynamic power control are enabled. The IR-UWB transmitters support new frequency hopping techniques providing more efficient spectrum usage and dynamic allocation of the spectrum when transmitting in highly congested frequency bands. Biphasic scrambling is also introduced for spectral line reduction.

Abstract: A method may be performed using a server. The method may include receiving an identity authentication request associated with a user, generating authentication information based on the identity authentication request, and generating candidate information based on the authentication information such that the authentication information is a subset of the candidate information. The candidate information may be displayed at a randomly selected location. The user may provide input through a graphic input interface to select the authentication information from among the candidate information.

Abstract: A method of identifying information during navigation is provided. Fork data is extracted from navigation data, the fork data corresponding to a road having a fork. A first node and at least two exit roads are extracted from the fork data, the at least two exit roads being roads in different directions. The fork data are identified as corresponding to a target fork in response to all of the at least two exit roads converging at the first node. A second node adjacent to the first node is queried in response to at least two exit roads not completely converging at the first node. The fork data are identified as corresponding to the target fork based on a distance between the first node and the second node meeting a preset condition.

Abstract: Within many applications impulse radio based ultra-wideband (IR-UWB) transmission offers significant benefits for very short range high data rate communications when compared with existing standards and protocols. In many of these applications the main design goals are very low power consumption and very low complexity design for easy integration and cost reduction. Digitally programmable IR-UWB transmitters using an on-off keying modulation scheme on a 0.13 microns CMOS process operating on 1.2 V supply and yielding power consumption as low as 0.9 mW at a 10 Mbps data rate with dynamic power control are enabled. The IR-UWB transmitters support new frequency hopping techniques providing more efficient spectrum usage and dynamic allocation of the spectrum when transmitting in highly congested frequency bands. Biphasic scrambling is also introduced for spectral line reduction.