Abstract: An improved Domino adder circuit has a carry evaluating logic, including a precharge transistor, an evaluation transistor, and three carry evaluating paths connected the precharge and evaluation transistors, and constituted by five N-channel Metal Oxide Silicon "NMOS" transistors which are connected to and controlled by three input signals respectively. The carry evaluating logic has a carry evaluating point positioned at the top of the carry evaluating paths. The improved Domino adder circuit further has a sum evaluating logic, including a precharge transistor, an evaluation transistor, and four sum evaluating paths connected between the precharge and evaluation transistors, and connected to and controlled by the three input signals respectively. The sum evaluating logic has a sum evaluating point at the top of the sum evaluating paths.