Abstract: The present disclosure provides an image processing method and apparatus, and an electronic device and a storage medium. The image processing method includes: inputting an initial depth map, a first confidence level of the initial depth map, an initial normal vector map and a second confidence level of the initial normal vector map into an optimizer; performing joint optimization on a depth map and a normal vector map, with an objective of minimizing a difference between an optimized depth map and the depth map before being optimized and a difference between an optimized normal vector map and the normal vector map before being optimized, and an objective of minimizing an error between local planes determined on the basis of a same region in the optimized depth map and the optimized normal vector map; and outputting the optimized depth map and the optimized normal vector map.

Abstract: The present disclosure discloses a reconfigurable processor and a configuration method. The reconfigurable processor includes a reconfiguration configuration unit and a reconfigurable array. The reconfiguration configuration unit is configured to provide, according to an algorithm matched with a current application scenario, reconfiguration information used for reconfiguring a computation structure in the reconfigurable array. The reconfigurable array includes at least two stages of computational arrays, the reconfigurable array is configured to connect, according to the reconfiguration information provided by the reconfiguration configuration unit, adjacent two stages of the computational arrays to form a data path pipeline structure satisfying computation requirements of the algorithm.

Abstract: Disclosed in the present invention are a data scheduling system, when data to be processed is transmitted from the first FIFO to a reconfigurable array, the first write pointer control component allocates a first write cache address; when the reconfigurable array writes a processing result into the second FIFO, the second write pointer control component allocates a second write cache address; when the processing result cached in the second FIFO is read by a system bus, the read pointer control component allocates a read cache address; the empty-state determination control component determines an empty-state of the second FIFO according to the second write cache address and the read cache address; and the full-state determination control component determines a full-state of the second FIFO according to the first write cache address and the read cache address.

Abstract: The present disclosure provides an image processing method and apparatus, and an electronic device and a storage medium. The image processing method includes: inputting an initial depth map, a first confidence level of the initial depth map, an initial normal vector map and a second confidence level of the initial normal vector map into an optimizer; performing joint optimization on a depth map and a normal vector map, with an objective of minimizing a difference between an optimized depth map and the depth map before being optimized and a difference between an optimized normal vector map and the normal vector map before being optimized, and an objective of minimizing an error between local planes determined on the basis of a same region in the optimized depth map and the optimized normal vector map; and outputting the optimized depth map and the optimized normal vector map.

Abstract: Disclosed is a hardware acceleration based automatic read control system and method for a serial peripheral interface (SPI). The automatic read control system includes an SPI module, an advanced peripheral bus (APB) module, an interrupt generation module, a direct memory access (DMA) controller, a state schedule control module, a register group module, a count signal generation module, a transmitted data buffer and a received data buffer; the state schedule control module, the register group module and the count signal generation module form a state machine system; and the state schedule control module controls automatic timed batch read of sensor data of the SPI according to configuration information of the register group module and counting and timing information of the count signal generation module.

Abstract: Disclosed is a hardware acceleration based automatic read control system and method for a serial peripheral interface (SPI). The automatic read control system includes an SPI module, an advanced peripheral bus (APB) module, an interrupt generation module, a direct memory access (DMA) controller, a state schedule control module, a register group module, a count signal generation module, a transmitted data buffer and a received data buffer; the state schedule control module, the register group module and the count signal generation module form a state machine system; and the state schedule control module controls automatic timed batch read of sensor data of the SPI according to configuration information of the register group module and counting and timing information of the count signal generation module.

Abstract: A scan mode is used in a voltage detection circuit. An oscillator in the circuit is always on and a system including the voltage detection circuit detects various abnormal conditions, such as overcharging, overdischarging and overcurrent one by one for some clocks. To reduce the power consumption, the voltage detection circuit is turned on only once for several clocks. The on-time is very short and lasts about only one tenth of a clock cycle time. In other times, the voltage detection circuit is turned off to save power consumption.