Abstract: A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

Abstract: A semiconductor integrated circuit having a resistor is disclosed in which the resistor is formed by a series connection of one element having a positive temperature coefficient and another element having a negative temperature coefficient.

Abstract: A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

Abstract: A semiconductor integrated circuit having a resistor is disclosed in which the resistor is formed by a series connection of one element having a positive temperature coefficient and another element having a negative temperature coefficient.

Abstract: A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

Abstract: A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

Abstract: A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

Abstract: A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

Abstract: A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

Abstract: A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

Abstract: Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios include the steps of forming a tunneling oxide layer on a face of a semiconductor substrate and then forming a forming a first conductive layer (e.g., doped polysilicon) on the tunneling oxide layer. A floating gate electrode mask is then patterned on the first conductive layer so as to expose a portion the first conductive layer. A second conductive layer is then patterned on the exposed portion of the first conductive layer and on sidewalls of the floating gate electrode mask, to define a concave or U-shaped floating gate electrode having conductive sidewall extensions. The sidewall extensions increase the effective area of the floating gate electrode and increase the capacitance coupling ratio which enables programming and erasing at reduced voltage levels. A first electrically insulating layer is then formed on the U-shaped floating gate electrode, opposite the tunneling oxide layer.

Abstract: A method of manufacturing a non-volatile memory device is provided. According to an aspect of this method, an isolation layer is formed on a semiconductor substrate including a cell array part and a peripheral circuit part. A floating gate pattern is formed exposing the semiconductor substrate in the peripheral circuit part with a tunnel oxide layer interposed between the floating gate pattern and the semiconductor substrate in the cell array part, and an interlayer insulating layer covering the floating gate pattern is formed. A control gate layer is formed, which covers the interlayer insulating layer and the semiconductor substrate in the peripheral circuit part while interposing a gate oxide layer between the control gate layer and the semiconductor substrate.

Abstract: A flash memory device for providing high integration and high-speed data access has string blocks arranged in a two-dimensional manner. Each string block has a plurality of strings, at least one bit line select line, a plurality of word lines, a plurality of source line select lines, a first dual-mode line, and a second dual-mode line. Each string is constructed such that at least one bit line select transistor, a plurality of unit memory cells, and a plurality of source line select transistors are connected in series. The bit line select lines are connected to respective gates of the bit line select transistors. The plurality of word lines are connected to respective control gates of the plurality of unit memory cells. The first dual-mode line is connected to one end of each of the strings in a first string block through a bit line contact, and the second dual-mode line is connected to other end of each of the strings in the first string block through a source line contact.

Abstract: A non-volatile memory device is disclosed in which a pair of two adjacent memory cell strings are commonly connected to one bit line and the memory cell strings are selectively driven to obtain a relatively wide pitch margin between two bit lines. The device has a conductive plate line which is located along each memory cell string or a pair of memory cell strings to drive memory cells thereof with a relatively low program voltage to a word line. The memory device comprises a plurality of memory cell strings which are arranged in parallel with one another and each of which extends in the same direction as a bit line 12, and a pair of two adjacent memory cell strings 11a and 11b are commonly connected to the bit line 12.