Abstract: A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.

Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to facilitate frequency locking of the SS-PLL.

Abstract: A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.

Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to facilitate frequency locking of the SS-PLL.

Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.

Abstract: A DTC circuit, includes: a DAC connected to a first node; a first switch connected between a first power source and a second node, and to provide a charge current to the second node according to a first switching signal; and a second switch connected between the first node and the second node, and to electrically connect the DAC to the second node according to a second switching signal. The DAC is to be charged to generate a voltage ramp corresponding to the charge current during a first DTC operational phase when the first and second switching signals have an active level to turn on the first and second switches, and to generate an input control word dependent voltage according to an input control word during a second DTC operational phase when the first and second switching signals have an inactive level to turn off the first and second switches.

Abstract: Methods and apparatuses are provided for fractional-N frequency synthesis using a phase-locked loop (PLL). A phase detector (PD) of the PLL determines a phase difference between a clock and a feedback clock (CLKFB). A low-pass loop filter of the PLL detects a control voltage based on the phase difference. A voltage-controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage. A sigma-delta modulator (SDM) of the PLL generates a division sequence ratio and a selection control signal based on a frequency command word. A multi-modulus divider (MMDIV) generates a first CLKFB and a second CLKFB based on the division sequence ratio and differential inputs of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

Abstract: Embodiments described herein provide a method for correcting a propagation delay induced error in an output of an asynchronous counter. An input clock is applied to the asynchronous counter. A gray-code count is generated by the asynchronous counter. The gray-code count is mapped to a binary count. An error component, indicative of a counting error induced by a propagation delay between the input clock and the binary count, is generated by taking an exclusive-OR operation over the gray-code count and the input clock. The error component is added to the binary count to generate an error-corrected binary count. The error-corrected binary count is output.

Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.

Abstract: A novel and useful millimeter-wave digitally controlled oscillator (DCO) that achieve a tuning range greater than 10% and fine frequency resolution less than 1 MHz. Switched metal capacitors are distributed across a passive resonator for tuning the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques are used that exploit an inductor and a transformer. A 60-GHz fine-resolution inductor-based DCO (L-DCO) and a 60 GHz transformer-coupled DCO (T-DCO), both fabricated in 90 nm CMOS, are disclosed. The phase noise of both DCOs is lower than ?90.5 dBc/Hz at 1 MHz offset across 56 to 62 GHz frequency range. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz.

Abstract: A novel and useful millimeter-wave digitally controlled oscillator (DCO) that achieve a tuning range greater than 10% and fine frequency resolution less than 1 MHz. Switched metal capacitors are distributed across a passive resonator for tuning the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques are used that exploit an inductor and a transformer. A 60-GHz fine-resolution inductor-based DCO (L-DCO) and a 60 GHz transformer-coupled DCO (T-DCO), both fabricated in 90 nm CMOS, are disclosed. The phase noise of both DCOs is lower than ?90.5 dBc/Hz at 1 MHz offset across 56 to 62 GHz frequency range. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz.