Abstract: Aspects of the subject technology provide miniaturization and improved power dissipation for communication systems that include a radio frequency power amplifier. In aspects, a radio frequency power amplifier may be mounted inside a cavity in a primary printed circuit board. Circuits related the power amplifier, such as output matching circuits, biasing circuits, and/or passive components, may be mounted on submodule printed circuit board that itself is mounted to the primary printed circuit board in a stacked configuration above the power amplifier and the cavity containing the power amplifier.

Abstract: Embodiments of the invention may provide systems and methods for minimizing phase deviation and/or amplitude modulation (AM)-to-phase modulation (PM) conversion for dynamic range, radio frequency (RF) non-linear amplifiers. In order to provide high dynamic range with reduced phase error, embodiments of the invention may utilize two separate paths for processing a signal. In particular, an input signal may be sampled and divided into each path. The first signal path may be used to shape a signal, and in particular, a voltage waveform at the load. The second signal path may be used for generating negative capacitances corresponding to the voltage waveform at the load. By combining the two signals at the load, a high-dynamic range, high-frequency, non-linear amplifier can be achieved that reduces phase error resulting from amplitude fluctuations with a relatively low unity-gain frequency (fT) process.

Abstract: Embodiments of the invention may be directed to a continuous analog phase shifter for radio frequency (RF) signals, which can be integrated on a CMOS process or another compatible process where inherent process-dependent passive components such as inductors and capacitors may have low quality factors. Insertion loss degradation for a given amount of phase shift may be compensated by using an active compensation circuit/device that smartly controls negative resistance generated from the compensation circuit/device to cancel out finite resistance of a network, leading to very small insertion loss variation. According to an example aspect of the invention, improved phase linearity and increased phase shift for a given size may be obtained by incorporating the compensation circuit/device. Thus, example analog phase shifters in accordance with example embodiments of the invention may have one or more of low insertion loss variation, small size, and good phase linearity over more than a 360 degree phase shift.

Abstract: Example driver circuits can utilize shared-charge recycling charge pump structures. In particular, an example shared-charge recycling process may be applied to a clock buffer and charge transfer cells of the charge pump in a driver circuit. An example recycling process may include recycling of shared charges between the capacitors/capacitances in the charge transfer cells. An example recycling process may use the charges in one or more capacitors to charge one or more other capacitors before the charges are wasted or otherwise discharged to ground. Such recycling may significantly reduce the power consumption of the charge pump while still providing a high output voltage level, according to an example embodiment of the invention.

Abstract: Embodiments of the invention may be directed to a continuous analog phase shifter for radio frequency (RF) signals, which can be integrated on a CMOS process or another compatible process where inherent process-dependent passive components such as inductors and capacitors may have low quality factors. Insertion loss degradation for a given amount of phase shift may be compensated by using an active compensation circuit/device that smartly controls negative resistance generated from the compensation circuit/device to cancel out finite resistance of a network, leading to very small insertion loss variation. According to an example aspect of the invention, improved phase linearity and increased phase shift for a given size may be obtained by incorporating the compensation circuit/device. Thus, example analog phase shifters in accordance with example embodiments of the invention may have one or more of low insertion loss variation, small size, and good phase linearity over more than a 360 degree phase shift.

Abstract: Embodiments of the invention may provide systems and methods for minimizing phase deviation and/or amplitude modulation (AM)-to-phase modulation (PM) conversion for dynamic range, radio frequency (RF) non-linear amplifiers. In order to provide high dynamic range with reduced phase error, embodiments of the invention may utilize two separate paths for processing a signal. In particular, an input signal may be sampled and divided into each path. The first signal path may be used to shape a signal, and in particular, a voltage waveform at the load. The second signal path may be used for generating negative capacitances corresponding to the voltage waveform at the load. By combining the two signals at the load, a high-dynamic range, high-frequency, non-linear amplifier can be achieved that reduces phase error resulting from amplitude fluctuations with a relatively low unity-gain frequency (fT) process.

Abstract: Systems and methods for provided for linearization systems and methods for variable attenuators. The variable attenuators can include series transistors along a main signal path from the input to output, as well as shunt transistors. A bootstrapping body bias circuit can be used with one or of the series transistors to allow the body of a connected transistor to swing responsive to a received RF input signal. As the RF signal increases and affects the gate-to-source voltage difference of a transistor, a bootstrapping body bias circuit can adaptively adjust the threshold voltage of the connected transistor and compensate the channel resistance variation resulting from gate-to-source voltage swing. The bootstrapping body bias circuit can be implemented using passive elements, active elements, or a combination thereof.

Abstract: Systems and methods may be provided for a CMOS RF antenna switch. The systems and methods for the CMOS RF antenna switch may include an antenna that is operative to transmit and receive signals over at least one radio frequency (RF) band, and a transmit switch coupled to the antenna, where the transmit switch is enabled to transmit a respective first signal to the antenna and disabled to prevent transmission of the first signal to the antenna. the systems and methods for the CMOS RF antenna switch may further include a receiver switch coupled to the antenna, where the receiver switch forms a filter when enabled and a resonant circuit when disabled, where the filter provides for reception of a second signal received by the antenna, and where the resonant circuit blocks reception of at least the first signal.

Abstract: A power amplifier system can include a plurality of driver amplifiers and a plurality of power amplifiers, where each driver amplifier and power amplifier includes at least one respective input port and at least one respective output port. The power amplifier system also includes a shared inductive device that provides common interstage matching between the respective output ports of the plurality of driver amplifiers and the respective input ports of the plurality of power amplifiers. The shared inductive device can be a shared inductor or a shared transformer.

Abstract: Systems and methods for provided for linearization systems and methods for variable attenuators. The variable attenuators can include series transistors along a main signal path from the input to output, as well as shunt transistors. A bootstrapping body bias circuit can be used with one or of the series transistors to allow the body of a connected transistor to swing responsive to a received RF input signal. As the RF signal increases and affects the gate-to-source voltage difference of a transistor, a bootstrapping body bias circuit can adaptively adjust the threshold voltage of the connected transistor and compensate the channel resistance variation resulting from gate-to-source voltage swing. The bootstrapping body bias circuit can be implemented using passive elements, active elements, or a combination thereof.

Abstract: A SPDT or SPMT switch may include a transformer having a primary winding and a secondary winding, where a first end of the secondary winding is connected to a single pole port, where a first end of the primary winding is connected to a first throw port; a first switch having a first end and a second end, where the first end is connected to ground; and a second switch, where a second end of the secondary winding is connected to both a second end of the first switch and a first end of the second switch, where a second end of the second switch is connected to a second throw port, where the first switch controls a first communication path between the single pole port and the first throw port, and where the second switch controls a second communication path between the second throw port and the single pole port.

Abstract: A power amplifier system can include a plurality of driver amplifiers and a plurality of power amplifiers, where each driver amplifier and power amplifier includes at least one respective input port and at least one respective output port. The power amplifier system also includes a shared inductive device that provides common interstage matching between the respective output ports of the plurality of driver amplifiers and the respective input ports of the plurality of power amplifiers. The shared inductive device can be a shared inductor or a shared transformer.

Abstract: A SPDT or SPMT switch may include a transformer having a primary winding and a secondary winding, where a first end of the secondary winding is connected to a single pole port, where a first end of the primary winding is connected to a first throw port; a first switch having a first end and a second end, where the first end is connected to ground; and a second switch, where a second end of the secondary winding is connected to both a second end of the first switch and a first end of the second switch, where a second end of the second switch is connected to a second throw port, where the first switch controls a first communication path between the single pole port and the first throw port, and where the second switch controls a second communication path between the second throw port and the single pole port.

Abstract: Systems, methods, and apparatuses are provided for linear envelope elimination and restoration transmitters that are based on the polar modulation operating in conjunction with the orthogonal recursive predistortion technique. The polar modulation technique enhances the battery life by dynamically adjusting the bias level. Further, the analog orthogonal recursive predistortion efficiently corrects amplitude and phase errors in radio frequency (RF) power amplifiers (PA) and enhances the PA output capability. Additionally, even-order distortion components are used to predistort the input signal in a multiplicative manner so that the effective correction bandwidth is greatly enhanced. Also, the predistortion scheme, which uses instantaneously feed-backed envelope distortion signals, allows for correction of any distortion that may occur within the correction loop bandwidth, including envelope memory effects.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SP4T switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz and 1.9 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate tuning to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. On the other hand, in the transmit switch, a body substrate tuning technique may be applied to maintain high power delivery to the antenna. Example embodiments of the CMOS antenna switch may provide for 31 dBm P 1 dB at both bands (e.g., 900 MHz and 1.8 GHz). In addition, a 0.9 dB and ?1.1 dB insertion loss at 900 MHz and 1.9 GHz, respectively, may be obtained according to example embodiments of the invention.

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Abstract: System and methods are provided for multi-path orthogonal recursive predistortion. The systems and methods may include generating a first orthogonal signal and a second orthogonal signal, where the first and second signals are orthogonal components of an input signal and processing, at a first predistortion module, the first orthogonal signal and a first error correction signal to generate a first predistorted signal.

Abstract: Systems and methods are disclosed for providing a linear polar transmitter. The systems and methods may include generating an input amplitude signal and an input phase signal, where the input amplitude signal and the input phase signal are orthogonal components of an input signal, and where the input amplitude signal and the input phase signal are generated on respective first and second signal paths. The systems and methods may also include processing the input amplitude signal along the first signal path using an amplitude error signal to generate a predistorted amplitude signal, and processing the input phase signal along the second signal path using an phase error signal to generate a predistorted phase signal.

Abstract: Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a ?60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.

Abstract: Embodiments of the invention may provide for a load regulation tuner that reduces the load regulation effect. The load regulation tuner may include a load current controlled current source that is responsive to a load current from a power transistor of a linear regulator, where the load current controlled current source includes a sensing transistor that generates a fraction of the load current as a sensed partial load current. The load regulation tuner may also include a resistor in parallel with a load current controlled current source, and where the paralleled resistor and the load current controlled current source form at least a portion of a feedback block that adjusts an operation of the linear regulator to provide a substantially constant load voltage.