Abstract: An audio amplifier includes a compensation unit, an output unit and a calibration unit. The compensation unit generates a compensation signal based on a digital input signal, a digital reference code, a mode signal and a digital approximation code. The output unit generates an output signal based on the compensated input signal. The calibration unit generates the digital approximation code based on the output signal and the mode signal. The digital approximation code includes a plurality of bits that are generated sequentially.

Abstract: An audio amplifier includes a compensation unit, an output unit and a calibration unit. The compensation unit generates a compensation signal based on a digital input signal, a digital reference code, a mode signal and a digital approximation code. The output unit generates an output signal based on the compensated input signal. The calibration unit generates the digital approximation code based on the output signal and the mode signal. The digital approximation code includes a plurality of bits that are generated sequentially.

Abstract: A half-bridge three-level pulse width modulation (PWM) amplifier includes a prescaling unit, a PWM generator configured to convert the input signal to a three-level PWM signal having a first level, a second level and a reference level and an output stage. The prescaling unit scales an input signal according to at least one gain value to provide a scaled signal. The PWM generator varies the width of pulses having the first level and varies the width of pulses having a second level based on the scaled signal. The output stage drives an output node to a level of a first power supply voltage, a second power supply voltage or a third power supply voltage based on the three-level PWM signal. The output node is connected to a load. The magnitude of the at least one gain value compensates for variations of power supply voltages.

Abstract: A circuit of reducing a pop-up noise in a digital amplifier includes a switch unit and a switch signal generator. The switch unit is coupled in parallel to an output load between an output node of the digital amplifier and a reference node. The switch unit controls a current flowing through the output load by forming a conduction path between the output node and the reference node in response to a switch signal. The switch signal generator generates the switch signal in response to a switch control signal indicating a power-on or a power-off. The pop-up noise is reduced by the conduction path that is formed when the digital amplifier is powered on or off.

Abstract: An audio amplifier includes a compensation unit, an output unit and a calibration unit. The compensation unit generates a compensation signal based on a digital input signal, a digital reference code, a mode signal and a digital approximation code. The output unit generates an output signal based on the compensated input signal. The calibration unit generates the digital approximation code based on the output signal and the mode signal. The digital approximation code includes a plurality of bits that are generated sequentially.

Abstract: A half-bridge three-level pulse width modulation (PWM) amplifier includes a prescaling unit, a PWM generator configured to convert the input signal to a three-level PWM signal having a first level, a second level and a reference level and an output stage. The prescaling unit scales an input signal according to at least one gain value to provide a scaled signal. The PWM generator varies the width of pulses having the first level and varies the width of pulses having a second level based on the scaled signal. The output stage drives an output node to a level of a first power supply voltage, a second power supply voltage or a third power supply voltage based on the three-level PWM signal. The output node is connected to a load. The magnitude of the at least one gain value compensates for variations of power supply voltages.

Abstract: A circuit of reducing a pop-up noise in a digital amplifier includes a switch unit and a switch signal generator. The switch unit is coupled in parallel to an output load between an output node of the digital amplifier and a reference node. The switch unit controls a current flowing through the output load by forming a conduction path between the output node and the reference node in response to a switch signal. The switch signal generator generates the switch signal in response to a switch control signal indicating a power-on or a power-off. The pop-up noise is reduced by the conduction path that is formed when the digital amplifier is powered on or off.

Abstract: A digital base booster (DBB) for reducing hardware by using an arithmetic processor is provided. Instead of using a conventional IIR filter having a cascade structure including a plurality of partial building blocks, the digital base booster using an arithmetic processor includes first internal data, an inputting portion, a data assigner, an arithmetic portion, and an output data storing device. The first internal data is the output data of the arithmetic portion. The inputting portion includes a plurality of multi-bit registers, thereby storing input data and the first internal data and outputting the stored data in a predetermined signal. The data assigner selects one output data from a plurality of output data of the inputting portion. The arithmetic portion performs an arithmetic operation on the output data of the data assigner and data stored in the arithmetic portion, compensates for and stores a round-off error of the data output by the operation, and outputs the first internal data.

Abstract: A digital base booster (DBB) for reducing hardware by using an arithmetic processor is provided. Instead of using a conventional IIR filter having a cascade structure including a plurality of partial building blocks, the digital base booster using an arithmetic processor includes first internal data, an inputting portion, a data assigner, an arithmetic portion, and an output data storing device. The first internal data is the output data of the arithmetic portion. The inputting portion includes a plurality of multi-bit registers, thereby storing input data and the first internal data and outputting the stored data in a predetermined signal. The data assigner selects one output data from a plurality of output data of the inputting portion. The arithmetic portion performs an arithmetic operation on the output data of the data assigner and data stored in the arithmetic portion, compensates for and stores a round-off error of the data output by the operation, and outputs the first internal data.