Abstract: A memory system includes a controller that recognizes, as a command, a signal received immediately after a chip select signal is received from a host device, and a memory that includes a plurality of blocks. When the command is a first command, the controller outputs to the host device, information indicating whether at least one of a write operation and an erase operation with respect to at least one particular block is prohibited.

Abstract: According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. When performing a first operation of concurrently executing outputting of first data read from the first memory cell array to an outside and reading of second data different from the first data from the first memory array, an interface circuit is configured to output information based on the error detected with respect to the first data to the outside.

Abstract: According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. When performing a first operation of concurrently executing outputting of first data read from the first memory cell array to an outside and reading of second data different from the first data from the first memory array, an interface circuit is configured to output information based on the error detected with respect to the first data to the outside.

Abstract: A memory system includes a controller that recognizes, as a command, a signal received immediately after a chip select signal is received from a host device, and a memory that includes a plurality of blocks. When the command is a first command, the controller outputs to the host device, information indicating whether at least one of a write operation and an erase operation with respect to at least one particular block is prohibited.

Abstract: Disclosed herein is a nonvolatile semiconductor memory device containing a semiconductor layer, a block insulating layer, an organic molecular layer which is formed between the semiconductor layer and the block insulating layer, and a control gate electrode formed on the block insulating layer. The organic molecular layer contains first organic molecules and second organic molecules, such that the first organic molecule has a first alkyl chain or a first alkyl halide chain on the semiconductor layer side and a charge trapping unit on the block insulating layer side, and the second organic molecule has a second alkyl chain or a second alkyl halide chain on the semiconductor layer side and a hydroxy group, an ether group, a carboxyl group or an ester group on the block insulating layer side.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating layer; an organic molecular layer, which is formed between the semiconductor layer and the block insulating layer, and contains first organic molecules and second organic molecules, and in which the first organic molecule has a first alkyl chain or a first alkyl halide chain on the semiconductor layer side and a charge trapping unit on the block insulating layer side, and the second organic molecule has a second alkyl chain or a second alkyl halide chain on the semiconductor layer side and a hydroxy group, an ether group, a carboxyl group or an ester group on the block insulating layer side; and a control gate electrode formed on the block insulating layer.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating layer; an organic molecular layer, which is formed between the semiconductor layer and the block insulating layer, and contains first organic molecules and second organic molecules, and in which the first organic molecule has a first alkyl chain or a first alkyl halide chain on the semiconductor layer side and a charge trapping unit on the block insulating layer side, and the second organic molecule has a second alkyl chain or a second alkyl halide chain on the semiconductor layer side and a hydroxy group, an ether group, a carboxyl group or an ester group on the block insulating layer side; and a control gate electrode formed on the block insulating layer.