Abstract: An apparatus includes a first die connected to a second die through a die-to-die (D2D) interface. The first die includes a first interconnect configured to provide first lanes communicating with the second die to the D2D interface, the first interconnect includes a first logic circuit configured to indicate a correlation between a number of chiplet dies connected to the first lanes and connected signal pins from among a plurality of signal pins of the connected chiplet dies. The second die includes the number of connected chiplet dies each including a second interconnect configured to provide second lanes to the D2D interface from each of the connected chiplet dies. The second lanes are configured to be set according to a number of the connected signal pins of the connected chiplet dies.

Abstract: A semiconductor package may include a package substrate; a plurality of upper dies on an upper side of the package substrate and arranged so as not to overlap each other vertically; a plurality of electrical connection structures between the plurality of upper dies and the package substrate and electrically connected to the package substrate; a lower die on the package substrate and arranged so as not to vertically overlap with the plurality of electrical connection structures; and a plurality of overlapped electrical connection structures arranged between the plurality of upper dies and an upper surface of the lower die and electrically connected to the upper surface of the lower die. Each of the plurality of upper dies may include a plurality of memory dies that overlap each other vertically.

Abstract: A semiconductor apparatus includes a semiconductor layer having a first surface and a second surface that is opposite to the first surface; a first wire structure on the first surface of the semiconductor layer; a second wire structure on the second surface of the semiconductor layer; a through via that extends through the semiconductor layer and is electrically connected to the first wire structure and the second wire structure; a first semiconductor element layer that is adjacent to the first surface of the semiconductor layer and in the semiconductor layer; and a second semiconductor element layer that is adjacent to the second surface of the semiconductor layer and in the semiconductor layer.

Abstract: An apparatus includes a first die connected to a second die through a die-to-die (D2D) interface. The first die includes a first interconnect configured to provide first lanes communicating with the second die to the D2D interface, the first interconnect includes a first logic circuit configured to indicate a correlation between a number of chiplet dies connected to the first lanes and connected signal pins from among a plurality of signal pins of the connected chiplet dies. The second die includes the number of connected chiplet dies each including a second interconnect configured to provide second lanes to the D2D interface from each of the connected chiplet dies. The second lanes are configured to be set according to a number of the connected signal pins of the connected chiplet dies.

Abstract: A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory devide, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing.