Patents by Inventor Wanjun Chen

Wanjun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12563869
    Abstract: A light emitting diode device includes an epitaxial layered structure and first and second electrodes that are disposed on the epitaxial layered structure. The second electrode includes a body portion and at least one extending portion connected to the body portion and extending in a direction away from the body portion. The extending portion includes at least one curved section. A projection of the curved section on the epitaxial layered structure includes first and second curved sides that are opposite to each other and that are curved in an identical direction. The first curved side has a first imaginary center of curvature, and the second curved side has a second imaginary center of curvature. A distance between the first imaginary center of curvature and the second imaginary center of curvature is equal to or smaller than 5 ?m.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: February 24, 2026
    Assignee: QUANZHOU SANAN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Linhua Cao, Wanjun Chen, Huining Wang, Heying Tang, Chunlan He, Lili Jiang, Liming Zhang, Renlong Yang, Chung-Ying Chang
  • Publication number: 20250337214
    Abstract: The present disclosure provides a semiconductor laser package and module. The package and module include a pin, a tube holder, a tube tongue, a heat sink, and a laser. A packaging form includes at least one of a plastic-encapsulated package and module, a transistor outline can (TO-CAN)-type package and module, and a chip-on-submount (COS) package and module. The package and module have a thermal conductance gradient. A thermal conductance of the tube holder is a, a thermal conductance of the tube tongue is b, a thermal conductance of the heat sink is c, and a thermal conductance of the laser is d, wherein the thermal conductance gradient is one of d?a?b?c, d?a?c?b, a?d?b?c, or a?d?c?b.
    Type: Application
    Filed: May 7, 2024
    Publication date: October 30, 2025
    Applicant: ANHUI GAN SEMICONDUCTOR CO., LTD.
    Inventors: Jinjian ZHENG, Shuiqing LI, Heqing DENG, Feilin XUN, Jiangyong ZHANG, Xin CAI, Jiabin LAN, Xiaoqin LI, Zhiyong HU, Wanjun CHEN
  • Publication number: 20250141191
    Abstract: The present disclosure provides a semiconductor green laser. The semiconductor green laser, from bottom to top, comprising a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer, and an upper limiting layer. The active layer is a quantum well composed of well layers and barrier layers. Each of the well layers includes any one of AlInGaN, AlInN, AlGaN, AlN, InN, InGaN, and GaN, or any combination thereof. Each of the barrier layers includes any one of AlInGaN, AlInN, AlGaN, AlN, InN, InGaN, and GaN, or any combination thereof. An electron effective mass of each of the well layers is less than an electron effective mass of each of the barrier layers. A spontaneous polarization coefficient of each of the well layers is less than a spontaneous polarization coefficient of each of the barrier layers.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 1, 2025
    Applicant: ANHUI GAN SEMICONDUCTOR CO., LTD.
    Inventors: Jinjian ZHENG, Shuiqing LI, Xin CAI, Wanjun CHEN, Jiabin LAN, Jiangyong ZHANG
  • Publication number: 20250141190
    Abstract: Disclosed is a semiconductor laser, from bottom to top, comprising: a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer, and an upper limiting layer. The lower limiting layer is composed of at least one of AllnGaN, AllnN, AlGaN, InN, AlN, InGaN, and GaN. A thickness of the lower limiting layer is denoted as x, and 10 angstroms?x?90,000 angstroms. The lower limiting layer includes a first lower limiting layer, a second lower limiting layer, and a third lower limiting layer. The lower limiting layer forms an electron saving structure and a stress regulating structure to regulate a carrier distribution and a stress distribution of the active layer, thereby reducing a threshold current and improving a slope efficiency of the laser.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 1, 2025
    Applicant: ANHUI GAN SEMICONDUCTOR CO., LTD.
    Inventors: Jinjian ZHENG, Shuiqing LI, Jiangyong ZHANG, Wanjun CHEN, Xin CAI
  • Publication number: 20250143016
    Abstract: Semiconductor light-emitting devices are provided, which includes a substrate, a Negative-type semiconductor, a quantum well, an electron-blocking layer, and a Positive-type semiconductor arranged in a sequential stack. The quantum well includes a first quantum well, a second quantum well, and a third quantum well. Optical parameters of the first quantum well, the second quantum well, and the third quantum well are distributed in a gradient in at least one direction. The quantum well includes a periodic structure consisting of a well layer and a barrier layer. A coefficient of thermal expansion of the well layer is smaller than or equal to that of the barrier layer. An elastic coefficient of the well layer is smaller than or equal to that of the barrier layer. A lattice constant of the well layer is greater than or equal to that of the barrier layer. A coefficient of spontaneous polarization of the well layer is smaller than or equal to that of spontaneous polarization of the barrier layer.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 1, 2025
    Applicant: ANHUI GAN SEMICONDUCTOR CO., LTD.
    Inventors: Shuiqing LI, Jinjian ZHENG, Jiabin LAN, Zhiyong HU, Wanjun CHEN
  • Patent number: 12119615
    Abstract: Disclosed is a semiconductor laser with a substrate mode suppression layer, comprising a substrate, a first limiting layer, a first waveguide layer, an active layer, a second waveguide layer, an electron blocking layer, and a second limiting layer sequentially stacked from bottom to top. A Si/C concentration ratio of an element Si to an element C of the substrate mode suppression layer?that of the first sub-limiting layer?that of the second sub-limiting layer. An In/Al concentration ratio of an element In to an element Al of the substrate mode suppression layer?that of the first sub-limiting layer?that of the second sub-limiting layer. An H/C concentration ratio of an element H to an element C of the substrate mode suppression layer?that of the second sub-limiting layer?that of the first sub-limiting layer.
    Type: Grant
    Filed: April 17, 2024
    Date of Patent: October 15, 2024
    Assignee: ANHUI GAN SEMICONDUCTOR CO., LTD.
    Inventors: Shuiqing Li, Hongzhu Kan, Jinjian Zheng, Xinghe Wang, Xin Cai, Wanjun Chen, Jiangyong Zhang, Jun Huang, Zihan Liu
  • Publication number: 20240332894
    Abstract: Disclosed is a semiconductor laser with a substrate mode suppression layer, comprising a substrate, a first limiting layer, a first waveguide layer, an active layer, a second waveguide layer, an electron blocking layer, and a second limiting layer sequentially stacked from bottom to top. A Si/C concentration ratio of an element Si to an element C of the substrate mode suppression layer?that of the first sub-limiting layer?that of the second sub-limiting layer. An In/Al concentration ratio of an element In to an element Al of the substrate mode suppression layer?that of the first sub-limiting layer?that of the second sub-limiting layer. An H/C concentration ratio of an element H to an element C of the substrate mode suppression layer?that of the second sub-limiting layer?that of the first sub-limiting layer.
    Type: Application
    Filed: April 17, 2024
    Publication date: October 3, 2024
    Applicant: ANHUI GAN SEMICONDUCTOR CO., LTD.
    Inventors: Shuiqing LI, Hongzhu KAN, Jinjian ZHENG, Xinghe WANG, Xin CAI, Wanjun CHEN, Jiangyong ZHANG, Jun HUANG, Zihan LIU
  • Publication number: 20230036698
    Abstract: A reverse blocking gallium nitride (GaN) high electron mobility transistor includes, sequentially stacked from bottom to top, a substrate, a nucleation layer, a buffer layer, a barrier layer, a dielectric layer. The buffer layer and the barrier layer form a heterojunction structure. The barrier layer is provided with at least two p-GaN structures. The barrier layer is provided with a source metal at one end and a drain metal at the other end, source metal forms ohmic contact and drain metal forms Schottky contact with AlGaN barrier, respectively. In forward conduction, the two-dimensional electron gas below the spaced p-GaN structure connected to the drain metal is conductive, and a turn-on voltage of the device is low. During reverse blocking, the two-dimensional electron gas at the spaced p-GaN structure is rapidly depleted under reverse bias, to form a depletion region, so that the blocking capability of the device is improved.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 2, 2023
    Applicants: University of Electronic Science and Technology of China, Institute of Electronic and Information Engineering of UESTC in Guangdong
    Inventors: Ruize SUN, Wanjun CHEN, Chao LIU, Pan LUO, Fangzhou WANG
  • Publication number: 20200211861
    Abstract: A die bonding process for manufacturing a semiconductor device includes the steps of: a) preparing a semiconductor structure and a substrate, b) mounting an electrode structure on the semiconductor structure to form a semiconductor component, c) forming a protective component at a die bonding region, and d) mounting the semiconductor component on the substrate via a die bonding technique. The protective component is made of an adsorbent material which has a greater adsorption capability for a suspended pollutant around the semiconductor device than an adsorption capability for the suspended pollutant of a material for the electrode structure.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Inventors: Feng WANG, Wanjun CHEN, Su-Hui LIN, Ling-Yuan HONG, Quan LIN, Yu ZHAN, Chen-Ke HSU
  • Patent number: 10672896
    Abstract: The present invention relates to the field of semiconductor switches, and relates more particularly to a GaN-based bidirectional switch device. The present invention provides a gate-controlled tunneling bidirectional switch device without Ohmic-contact, which avoids a series of negative effects (such as current collapse, incompatibility with traditional CMOS process) caused by the high temperature ohm annealing process. Each insulated gate structure near schottky-contact controls the band structure of the schottky-contact to change the working state of the device, realizing the bidirectional switch's ability of bidirectional conducting and blocking. Due to the only presence of schottky in this invention, no heavy elements such as gold is needed, and this device is compatible with traditional CMOS technology.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 2, 2020
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Wanjun Chen, Yijun Shi, Jie Liu, Xingtao Cui, Guanhao Hu, Chao Liu, Qi Zhou, Bo Zhang
  • Publication number: 20180158936
    Abstract: The present invention relates to the field of semiconductor switches, and relates more particularly to a GaN-based bidirectional switch device. The present invention provides a gate-controlled tunneling bidirectional switch device without Ohmic-contact, which avoids a series of negative effects (such as current collapse, incompatibility with traditional CMOS process) caused by the high temperature ohm annealing process. Each insulated gate structure near schottky-contact controls the band structure of the schottky-contact to change the working state of the device, realizing the bidirectional switch's ability of bidirectional conducting and blocking. Due to the only presence of schottky in this invention, no heavy elements such as gold is needed, and this device is compatible with traditional CMOS technology.
    Type: Application
    Filed: September 5, 2017
    Publication date: June 7, 2018
    Applicant: University of Electronic Science and Technology of China
    Inventors: Wanjun CHEN, Yijun SHI, Jie LIU, Xingtao CUI, Guanhao HU, Chao LIU, Qi ZHOU, Bo ZHANG
  • Patent number: 8076699
    Abstract: Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: December 13, 2011
    Assignee: The Hong Kong Univ. of Science and Technology
    Inventors: Jing Chen, Wanjun Chen, Chunhua Zhou
  • Publication number: 20100019279
    Abstract: Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers.
    Type: Application
    Filed: March 31, 2009
    Publication date: January 28, 2010
    Applicant: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jing CHEN, Wanjun CHEN, Chunhua ZHOU