Abstract: A display panel has sub-pixel regions. The display panel includes an optical device layer, an adhesive layer and a light adjustment layer. The optical device layer includes a buffer layer and light-emitting units, a light-emitting unit is located in an opening region of a corresponding sub-pixel region, and the buffer layer is located on a light-exit surface of the light-emitting units. The adhesive layer is located on a side of the buffer layer away from the light-emitting units, a refractive index n2 of the adhesive layer being less than a refractive index n1 of the buffer layer. The light adjustment layer is located on the side of the buffer layer, and is configured such that when light emitted by the light-emitting units enters into the buffer layer, at least part of light with a refraction angle greater than or equal to arc ? sin ? n ? 2 n ? 1 enters the adhesive layer through the light adjustment layer.

Abstract: A pixel driving circuit includes a data writing circuit, a light-emitting control circuit, a switching circuit and a light-emitting diode chip. The data writing circuit is electrically connected to a first scanning signal terminal, a data signal terminal and a first node. The light-emitting control circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to a second node. The switching circuit includes switching transistors. The light-emitting diode chip is electrically connected to the second node. The light-emitting diode chip includes light-emitting portions. The light-emitting diode chip is configured to drive the light-emitting portions to emit light in different periods of time respectively or drive at least two light-emitting portions to emit light in a same period of time. At least part of the light-emitting portions are sequentially connected in series through at least one switching transistor.

Abstract: A display panel and a display device are provided. The display panel includes a plurality of display units, each display unit includes a transparent area, and the display panel further includes a base substrate and a composite functional layer. The composite functional layer is provided on a side of the base substrate and has a first through-hole formed therein, and the first through-hole is provided in the transparent area. The composite functional layer includes a composite transparent layer and a light-shielding layer. The composite transparent layer includes a plurality of transparent functional layers, and includes a light-transmitting part surrounding the first through-hole. An orthographic projection of the light-shielding layer on the base substrate covers an orthographic projection of at least a portion of the light-transmitting part on the base substrate.

Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of subpixels. A respective subpixel of the plurality of subpixels includes n1 number of main light emitting elements; n1 number of main pixel driving circuits configured to drive light emission in the n1 number of main light emitting elements; n2 number of auxiliary light emitting elements; n2 number of auxiliary pixel driving circuits configured to drive light emission in the n2 number of auxiliary light emitting elements; n1?1, and n2?1. A respective main pixel driving circuit of the n1 number of main pixel driving circuits includes a first driving transistor. A respective auxiliary pixel driving circuit of the n2 number of auxiliary pixel driving circuits includes a second driving transistor.

Abstract: A scan circuit is provided. The scan circuit includes a plurality of scan units in a plurality of stages, respectively. A respective scan unit of the plurality of scan units includes an output subcircuit. The output subcircuit includes a first switch transistor and a second switch transistor. A source electrode of the first switch transistor is coupled to a third terminal configured to receive a first clock signal. A drain electrode of the first switch transistor is coupled to a first output terminal configured to output a first control signal. A source electrode of the second switch transistor is coupled to a fourth terminal configured to receive the third clock signal. A drain electrode of the second switch transistor is coupled to a second output terminal configured to output a second control signal. Gate electrodes of the first switch transistor and the second switch transistor are coupled to a first node.

Abstract: The embodiment of the present disclosure provides a display panel, which includes an array substrate, a counter substrate and a spacer. The array substrate includes a base substrate and a plurality of signal lines on the base substrate. The plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines. The plurality of first signal lines and the plurality of second signal lines intersect each other to define a plurality of first regions. The plurality of first regions include a plurality of first pixel regions, at least one second pixel region and at least one redundant region. The first signal line extends along a first direction, the second signal line includes a body portion extending along a second direction, at least one second signal line further includes a bending portion connected to the body portion.

Abstract: A display panel, a method for driving a display panel, and a display apparatus are provided. The display panel includes a first base substrate and a plurality of pixels on one side of the first base substrate. Each pixel includes: a plurality of pixel sub-electrodes independent from each other and configured to form an electric field with an included angle greater than 0 with respect to a direction perpendicular to the first base substrate under control of incompletely same driving signals; a common electrode on a side of the pixel electrode away from the first base substrate; and an electrophoretic liquid layer between the pixel electrode and the common electrode, including a plurality of charged particles therein.

Abstract: A display method is provided. The display method includes providing a display panel having a plurality of subpixels, a respective subpixel of the plurality of subpixels including a first area, n1 number of second areas, and n2 number of third areas, the first area being between the n1 number of second areas and the n2 number of third areas, n1?1, and n2?1; for displaying a first frame of image, controlling light emission of the respective subpixel to be limited in the first area, m1 number of the n1 number of second areas, and m2 number of the n2 number of third areas; and for displaying a second frame of image, controlling light emission of the respective subpixel to be limited in the first area, ml? number of the n1 number of second areas, and m2? number of the n2 number of third areas.

Abstract: A pixel driving circuit includes a data writing circuit, a light-emitting control circuit and a light-emitting diode chip. The data writing circuit is electrically connected to a first scanning signal terminal, a data signal terminal and a first node. The light-emitting control circuit is electrically connected to the first node, an enable signal terminal, a first voltage signal terminal and a second node, and is configured to transmit a first voltage signal received at the first voltage signal terminal to the second node. The light-emitting diode chip is electrically connected to the second node and a second voltage signal terminal. The light-emitting diode chip includes a plurality of light-emitting portions. The light-emitting diode chip is configured to drive the plurality of light-emitting portions to emit light in different periods of time respectively or drive at least two light-emitting portions to emit light in a same period of time.

Abstract: A light-emitting device includes a first semiconductor layer, a light-emitting functional layer and a second semiconductor layer that are stacked. The first semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The light-emitting functional layer includes a first light-emitting pattern and a second light-emitting pattern spaced apart. The second semiconductor layer includes a third semiconductor pattern and a fourth semiconductor pattern spaced apart. Orthographic projections of the first semiconductor pattern, the first light-emitting pattern and the third semiconductor pattern on a reference plane at least partially overlap to form a first light-emitting portion. Orthographic projections of the second semiconductor pattern, the second light-emitting pattern and the fourth semiconductor pattern on the reference plane at least partially overlap to form a second light-emitting portion.

Abstract: The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

Abstract: A light-emitting device, a light-emitting substrate, and a method for manufacturing the light-emitting device. The light-emitting device includes at least one light-emitting structure. The light-emitting structure includes: a first semiconductor layer; a light-emitting layer; a second semiconductor layer, doping ions of the second semiconductor layer and a first semiconductor layer being oppositely charged; a barrier structure provided with an opening for exposing the second semiconductor layer, the orthographic projection of the opening on the base substrate being located in the orthographic projection of the light-emitting layer on the base substrate, and the area of the opening being smaller than that of the light-emitting layer; and a landing electrode located on the side of the barrier structure facing away from the second semiconductor layer, the landing electrode being in contact with the second semiconductor layer by means of the opening.

Abstract: The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

Abstract: A pixel driving circuit includes a data writing circuit, a light-emitting control circuit and a light-emitting diode chip. The data writing circuit is electrically connected to a first scanning signal terminal, a data signal terminal and a first node. The light-emitting control circuit is electrically connected to the first node, an enable signal terminal, a first voltage signal terminal and a second node, and is configured to transmit a first voltage signal received at the first voltage signal terminal to the second node. The light-emitting diode chip is electrically connected to the second node and a second voltage signal terminal. The light-emitting diode chip includes a plurality of light-emitting portions. The light-emitting diode chip is configured to drive the plurality of light-emitting portions to emit light in different periods of time respectively or drive at least two light-emitting portions to emit light in a same period of time.

Abstract: The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

Abstract: A display panel has a display region and a fan-out lead region, the fan-out lead region is located within the display region. The display panel comprises a base, a pixel circuit layer, a plurality of fan-out leads disposed between the base and the pixel circuit layer and located in the fan-out lead region, and an electrical field shielding pattern disposed between the pixel circuit layer and a film layer in which the plurality of fan-out leads are located. The pixel circuit layer includes a plurality of pixel circuits, at least one pixel circuit is located in the fan-out lead region. At least one fan-out lead is electrically connected to the pixel circuits. Orthographic projection of active layer patterns of transistors of the pixel circuit located in the fan-out lead region on the base are located within an orthographic projection of the electric field shielding pattern on the base.

Abstract: A display substrate and a fabrication method thereof, and a display device. The display substrate includes a first pixel unit and a second pixel unit. The first pixel unit includes a first electrode and a first light-emitting layer that are stacked; the second pixel unit includes a second electrode and a second light-emitting layer that are stacked; an effective light-emitting area of the first light-emitting layer is unequal to an effective light-emitting area of the second light-emitting layer; and in a direction directly facing a display side of the display substrate, a light-reflecting area of the first electrode that is exposed in the first pixel unit is equal to a light-reflecting area of the second electrode that is exposed in the second pixel unit. The display substrate may suppress a color shift defect.

Abstract: The present disclosure relates to a display panel and a terminal device. The display panel includes a display region. At least a part of the display region is a transparent region. The transparent region has a plurality of pixel rows distributed along a column direction, and each of the plurality of pixel rows includes pixels and transparent portions arranged in a row direction. The pixel rows include first pixel rows and second pixel rows, transparent portions each arranged between two adjacent pixels in each of the first pixel rows are first transparent portions, and transparent portions each arranged between two adjacent pixels in each of the second pixel rows are second transparent portions. A width of each of the first transparent portions in the row direction is greater than a width of each of the second transparent portions in the row direction.

Abstract: A pixel circuit, a pixel driving method, and a display device are provided. The pixel circuit includes a light emitting element, a first voltage control circuit, a second voltage control circuit, a driving circuit, a first energy storage circuit, a data writing circuit, and a reset circuit. The first voltage control circuit includes a first control transistor, the driving circuit includes a driving transistor, and a difference between a threshold voltage of the first control transistor and a threshold voltage of the driving transistor is within a first range. The first voltage control circuit controls a potential of a first control node under control of a reset control signal; and the second voltage control circuit controls a potential of a second control node under control of the potential of the first control node.

Abstract: A pixel circuit, a pixel driving method, and a display device are provided. The pixel circuit includes a light emitting element, a first voltage control circuit, a second voltage control circuit, a driving circuit, a first energy storage circuit, a data writing circuit, and a reset circuit. The first voltage control circuit includes a first control transistor, the driving circuit includes a driving transistor, and a difference between a threshold voltage of the first control transistor and a threshold voltage of the driving transistor is within a first range. The first voltage control circuit controls a potential of a first control node under control of a reset control signal; and the second voltage control circuit controls a potential of a second control node under control of the potential of the first control node.