Patents by Inventor Wan-Soo Park

Wan-Soo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of operating a memory controller in which commands are stored in urgent or normal queues based on priority. a nonvolatile memory device including a buffer selector and a storage device thereof
    Patent number: 11989451
    Abstract: A method for operating a memory controller, the method including: receiving a first command from a first host; storing the first command in a queue; when the first command has a higher priority than a second command currently being performed, pausing an operation of the second command and performing a read operation of the first command; and continuing the operation of the second command after completion of the read operation of the first command.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: May 21, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wan-Soo Choi, Young Wook Kim, Hyun Seon Park
  • Methods of forming wiring structures including a plurality of metal layers
    Patent number: 9773699
    Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Jin Lee, Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Tsukasa Matsuda, Wan-Soo Park, Nae-In Lee, Jae-Won Chang, Eun-Ji Jung, Jeong-Ok Cha, Jae-Won Hwang, Jung-Ha Hwang
  • METHODS OF FORMING WIRING STRUCTURES
    Publication number: 20160293484
    Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
    Type: Application
    Filed: January 19, 2016
    Publication date: October 6, 2016
    Inventors: Jong-Jin Lee, Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Tsukasa Matsuda, Wan-Soo Park, Nae-In Lee, Jae-Won Chang, Eun-Ji Jung, Jeong-Ok Cha, Jae-Won Hwang, Jung-Ha Hwang