Patents by Inventor Ward G. Fillmore
Ward G. Fillmore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9362237Abstract: A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the dielectric material from passing into the region under the elevated portion of the air bridge structure.Type: GrantFiled: November 13, 2015Date of Patent: June 7, 2016Assignee: RAYTHEON COMPANYInventors: Ward G. Fillmore, Paul J. Duval
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Publication number: 20160071809Abstract: A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the to dielectric material from passing into the region under the elevated portion of the air bridge structure.Type: ApplicationFiled: November 13, 2015Publication date: March 10, 2016Applicant: RAYTHEON COMPANYInventors: Ward G. Fillmore, Paul J. Duval
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Patent number: 9219024Abstract: A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the dielectric material from passing into the region under the elevated portion of the air bridge structure.Type: GrantFiled: November 21, 2013Date of Patent: December 22, 2015Assignee: Raytheon CompanyInventors: Ward G. Fillmore, Paul J. Duval
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Publication number: 20150137310Abstract: A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the dielectric material from passing into the region under the elevated portion of the air bridge structure.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: Raytheon CompanyInventors: Ward G. Fillmore, Paul J. Duval
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Patent number: 8969176Abstract: A package for a plurality of semiconductor devices having: an electrical interconnect structure, comprising: an electrical interconnect structure; and an active device structure, comprising the plurality of semiconductor devices on an active device substrate. The electrical interconnect structure is bonded to the active device structure and the electrical interconnect structure provides electrical interconnection among the semiconductor devices.Type: GrantFiled: December 3, 2010Date of Patent: March 3, 2015Assignee: Raytheon CompanyInventors: Ward G. Fillmore, William J. Davis
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Patent number: 8653673Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.Type: GrantFiled: December 20, 2011Date of Patent: February 18, 2014Assignee: Raytheon CompanyInventors: Robert B. Hallock, William J. Davis, Yiwen Zhang, Ward G. Fillmore, Susan C. Trulli, Jason G. Milne
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Publication number: 20130154124Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: Raytheon CompanyInventors: Robert B. Hallock, William J. Davis, Yiwen Zhang, Ward G. Fillmore, Susan C. Trulli, Jason G. Milne
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Publication number: 20120139100Abstract: A package for a plurality of semiconductor devices having: an electrical interconnect structure, comprising: an electrical interconnect structure; and an active device structure, comprising the plurality of semiconductor devices on an active device substrate. The electrical interconnect structure is bonded to the active device structure and the electrical interconnect structure provides electrical interconnection among the semiconductor devices.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: Raytheon CompanyInventors: Ward G. Fillmore, William J. Davis
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Patent number: 8178391Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.Type: GrantFiled: September 23, 2011Date of Patent: May 15, 2012Assignee: Raytheon CompanyInventors: William J. Davis, Ward G. Fillmore, Scott MacDonald
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Publication number: 20120009735Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Applicant: Raytheon CompanyInventors: William J. Davis, Ward G. Fillmore, Scott MacDonald
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Patent number: 8035219Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.Type: GrantFiled: July 18, 2008Date of Patent: October 11, 2011Assignee: Raytheon CompanyInventors: William J. Davis, Ward G. Fillmore, Scott MacDonald
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Publication number: 20100013088Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor wafer, device exposing openings to expose the devices and electrical contact pad openings to expose electrical contact pads for devices; and mounting a support having a rigid dielectric layer formed on a selected portion of the support, such rigid dielectric layer comprising a second lithographically processable material, such rigid material being suspended over the device exposing openings and removed from portions of the support disposed over the electrical contacts pads openings in the first lithographically processable material. The support is released and removed from the second lithographically processable material, leaving the second photolithographically processable material bonded to the first photolithographically processable material.Type: ApplicationFiled: July 18, 2008Publication date: January 21, 2010Inventors: William J. Davis, Ward G. Fillmore, Scott MacDonald