Abstract: A hydration monitoring apparatus is disclosed. The hydration monitoring apparatus comprises at least one sensor and an analysis unit. The hydration monitoring apparatus may take at least one biometric, biological, and/or physiological measurement of an individual and measures the hydration level, dehydration level or status, or bodily fluid level of an individual. The hydration monitoring apparatus indicates the hydration level, dehydration level or status, or bodily fluid level of an individual based on one or more biometric, biological, and/or physiological measurements. In one embodiment of the invention, the hydration monitoring apparatus determines whether to inform the user of their hydration level, dehydration level or status, or bodily fluid level. In one embodiment the hydration monitoring apparatus further comprises an informing device that informs the individual that the individual is approaching dehydration.

Abstract: Encoding of quantum algorithm and devices therefrom are provided. The encoding includes receiving a unitary matrix operator representing the quantum algorithm, each row of the unitary matrix operator defining a superposition of basis state vectors for transforming input states to output states. The encoding also includes recording rows of the unitary matrix operator by applying, to a volume holographic element, a combination of an ith one of n reference waves and a superposition of n signal waves defined by the superposition defined in an ith row of the unitary matrix operator. The n signal waves are a first set of n plane waves lying on a first conical surface having a first half angle and the n reference waves are a second set of n plane waves lying on a second conical surface, concentric with the first conical surface, with a second half angle different that the first half angle.

Abstract: A 5-bit D-type master/slave counter/shift register with buffered outputs is disclosed. The counter implements the load, count up, count down, and reset functions and also has the capability to be reconfigured into an inverting serial shift register for Non-Functional Test (NFT) techniques. In addition, the fifth bit may optionally be removed from the counter logic and used as a parity bit, although it will be necessary to use some external logic to implement this parity function.

Abstract: A current mode arithmetic logic circuit utilizes a unique combination of a 4-bit and a 5-bit arithmetic logic unit for performing parity prediction and parity checking on an n-bit byte plus parity, in addition to performing 16 binary or 16 Boolean operations on two n-bit plus parity bytes.

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 5-bit bytes and generates a 5-bit binary output byte in accordance with the particular operational mode prescribed by a mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 5-bit input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F= is provided for zero detection purposes. In addition to the arithmetic or logic operations, the unit generates a parity of the half-sums signal HS, a parity of the half-parities signal HP, a parity of the carries signal PC, and a carry error signal CE. A carry-out signal COUT is also generated.

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 4-bit plus parity bytes and generates a 4-bit plus parity binary output byte in accordance with the particular operational mode prescribed by a binary operation mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 4-bit plus parity input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F=O is provided for zero detection purposes.

Abstract: An improved binary/binary coded decimal arithmetic logic unit employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal (BCD) data. The unit performs 16 binary and 2 decimal arithmetic operations and 16 Boolean operations on two 4-bit plus parity input fields. The particular operation is determined by a 5-bit mode control signal. A carry-in input CIN, duplicate carry-in input CIND, parity check PCK input, invert parity input IP, decimal mode signal D, and decimal add input DA are also provided. The device generates a binary output resultant of the operation defined by the mode control signal. In addition to the arithmetic or logic operations, the unit performs parity checking, parity carry, and parity prediction operations on 4-bit plus parity binary and BCD fields.

Abstract: A multiple-generating register generates one of several possible multiples of a binary number which is input thereto depending upon the informational content of a 3-bit control signal. For each data stage there exists a data selector circuit, a master/slave circuit, and an output buffer circuit. The device can be configured as an inverting shift register for test and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.