Abstract: A system comprising a chassis that includes a plurality of modules and a fan assembly disposed in a distal end of the chassis for drawing air in parallel pathways through the plurality of modules. At least one of the modules is a compute module having a thermal sensor disposed to sense the temperature of air flowing across a processor mounted on a motherboard. The system further comprises a fan controller receiving output from the thermal sensor, wherein the fan controller operates the fan assembly to cool the plurality of modules and maintain the thermal sensor output within an operating temperature range. The fan controller controls the fan speed according to predetermined thermal profile settings associated with one of the compute modules received in the chassis. For example, the predetermined thermal profile settings may include a minimum fan speed, a maximum fan speed, and control loop feedback settings.

Abstract: A system comprising a chassis that includes a plurality of modules and a fan assembly disposed in a distal end of the chassis for drawing air in parallel pathways through the plurality of modules. At least one of the modules is a compute module having a thermal sensor disposed to sense the temperature of air flowing across a processor mounted on a motherboard. The system further comprises a fan controller receiving output from the thermal sensor, wherein the fan controller operates the fan assembly to cool the plurality of modules and maintain the thermal sensor output within an operating temperature range. The fan controller controls the fan speed according to predetermined thermal profile settings associated with one of the compute modules received in the chassis. For example, the predetermined thermal profile settings may include a minimum fan speed, a maximum fan speed, and control loop feedback settings.

Abstract: A cache of a CPU/cache chip set, has a wide data path that is directly coupled, to a memory data bus having a narrow data path. The coupling is effected by a data transfer path comprising only conductors without any additional components that would introduce signal propagation delays. Cache data transfers are initiated by a cache controller. A bus controller provides data transfer control signals to transfer sets of data where each set has the same number of bits as the width of the memory bus. Data is transferred in burst cycles comprising a plurality of cache data transfer cycles. Each of the latter cycles comprises a plurality of memory bus cycles.