Abstract: A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: Described herein are systems and methods that reduce the latency which may occur when a level one (L1) cache issues a request to a level two (L2) cache, and that ensure that a translation requests sent to an L2 cache are flushed during a context switch. Such a system may include a work queue and a cache (such as an L2 cache). The work queue comprises a plurality of state machines, each configured to store a request for access to memory. The state machines can monitor requests that are stored in the other state machines and requests that the other state machines issue to the cache. A state machine only sends its request to the cache if another state machine is not already awaiting translation data relating to the that request. In this way, the request/translation traffic between the work queue and the cache can be significantly reduced.

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.

Abstract: A system and method by which a memory device can adapt or retrain itself in response to changes in its inputs or operating environment. The memory device, such as a DRAM, includes in its interface an embedded programmable component. The programmable component can be, for example and without limitation, a microprocessor, a microcontroller, or a microsequencer. A programmable component is programmed to make changes to the operation of the interface of the memory device, in response to changes in the environment of the memory device.

Abstract: The present invention is directed to a method, computer program product, and system for processing memory access requests. The method includes the following features. First, page table entries of a page table are organized into at least one fragment that maps logical memory to at least one of logical memory or physical memory. The at least one fragment has a fragment size and an alignment boundary. Then, a subset of the page table entries stored in one of a plurality of cache banks is accessed to determine a mapping between a first logical memory address and at least one of a second logical memory address or a physical memory address. Each cache bank is configured to store at least one page table entry corresponding to a fragment of a predetermined set of fragment sizes and a predetermined alignment boundary.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.