Abstract: A multilevel metallization is deposited on a microelectronic device base structure (40). The process includes depositing a glassy dielectric layer (48) of a thickness that is from about two to about three times as thick as the topography thickness (D) of the base structure (40). The glassy dielectric layer (48) is heated to a temperature above its glass transition temperature to flow the glassy dielectric layer (48). The glassy dielectric layer (48) is thinned to a preselected thickness, and a first patterned metallization layer (54) is deposited. The process further includes depositing an interlevel dielectric layer (58), dry etching the interlevel dielectric layer (58) to thin the interlevel dielectric layer (58) and, optionally, depositing additional interlevel dielectric layer (58') material to achieve a preselected thickness. A second patterned metallization layer (64) is deposited over the interlevel dielectric layer ( 58/58').

Abstract: The value of an unknown test temperature is measured by heating a test wafer (58) to the unknown temperature, measuring the surface electrical resistivity of the test wafer (58), and determining the value of the unknown temperature from the measured surface electrical resistivity. The test wafer (58) is prepared by providing an initial wafer (50), first ion implanting the initial wafer (50) with a first dose of an ionic species, and annealing the ion implanted initial wafer (50) at an annealing temperature. The preparation is completed by second ion implanting the annealed wafer with a second dose of the same ionic species as used in the first dose to form a test wafer, the second dose being lower than the first dose.