Abstract: A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution units for parallel pipelined execution, selects and provides operands as required for execution, and acts as a reorder buffer keeping the results of operations until the results can be safely committed. The scheduler is tightly coupled to execution pipelines and provides a large parallel path for initial operation stages which minimize pipeline bottlenecks and hold ups into and out of the execution units. The scheduler monitors the entries to determine when all operands required for execution of an operation are available and provides required operands to the execution units. The operands selected can be from a register file, a scheduler entry, or an execution unit.

Abstract: A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals. Each object is also provided member functions for initializing, for loading a new state and for generating a next state. These modules are collected in a linked list. In the beginning of simulation, each object is initialized as the linked list is traversed. Then, a consistent next state for the RTL model is obtained by generating a state next based on the initial state. Simulation proceeds by alternately traversing the linked list to load a new state into each module, and traversing the linked list to generate the next state for each module. The step of traversing the linked list to generate the next state of each module may require multiple executions to ensure convergence.

Abstract: Scan logic which tracks the relative age of stores with respect to a particular load (or of loads with respect to a particular store) allows at processor to hold younger stores until the completion of older loads (or to hold younger loads until completion of older stores). Embodiments of propagate-kill style lookahead scan logic or of tree-structured, hierarchically-organized scan logic constructed in accordance with the present invention provide store older and load older indications with very few gate delays, even in processor embodiments adapted to concurrently evaluate large numbers of operations. Operating in conjunction with the scan logic, address matching logic allows the processor to more precisely tailor its avoidance of load-store (or store-load) dependencies.

Abstract: A method for analyzing the performance of a logic circuit driven by a clock signal, such as a microprocessor, identifies a number of operations of interest in a logic circuit and represents the presence of each of such operations by a different symbol. One or more of these symbols are output for perusal at the end of each clock period of operation. In one embodiment, this method is applied to a register transfer level (RTL) simulation of an execution unit of a microprocessor. In that embodiment, the execution sequence of multiple instructions executing simultaneously in the execution unit was analyzed. Because each output symbol represents a summary of a large number of activities that occur in a single clock period of operation or simulation of a complex logic circuit, these symbols can be tabulated in a format that allows a designer of the complex logic circuit to easily spot an unexpected pattern of operation, or an error condition.

Abstract: A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution units for parallel pipelined execution, selects and provides operands as required for execution, and acts as a reorder buffer keeping the results of operations until the results can be safely committed. The scheduler is tightly coupled to execution pipelines and provides a large parallel path for initial operation stages which minimize pipeline bottlenecks and hold ups into and out of the execution units. The scheduler monitors the entries to determine when all operands required for execution of an operation are available and provides required operands to the execution units. The operands selected can be from a register file, a scheduler entry, or an execution unit.

Abstract: A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a hierarchy of objects ("modules") each having representation of state elements, input signals, output signals and internal signals. Each object is also provided member functions for initializing, for loading a new state and for generating a next state. These modules are collected in a linked list. In the beginning of simulation, each object is initialized as the linked list is traversed. Then, a consistent next state for the RTL model is obtained by generating a state next based on the initial state. Simulation proceeds by alternately traversing the linked list to load a new state into each module, and traversing the linked list to generate the next state for each module. The step of traversing the linked list to generate the next state of each module may require multiple executions to ensure convergence.

Abstract: Multiple functional units of a computer system that typically access a secondary cache and the main memory system independently and simultaneously are simulated using RTL models which create such accesses using a random process. In one embodiment, an RTL model of each functional unit generates accesses to the cache memory according to a programmable frequency. The RTL models of these functional units also generate addresses which fall within programmable address limits and tag limits. In one embodiment, the functional units include data and instruction table lookaside buffers which traverse a two-level address translation scheme.

Abstract: Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in accordance with the present invention to hold younger stores until the completion of older loads (and to hold younger loads until completion of older stores). Address matching logic allows a load-store execution controller constructed in accordance with the present invention to avoid load-store (and store-load) dependencies. Propagate-kill scan chains supply the relative age indications of loads with respect to stores (and of stores with respect to loads).