Patents by Inventor Warren GROSS

Warren GROSS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100074381
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Application
    Filed: September 25, 2009
    Publication date: March 25, 2010
    Applicant: The Royal Institution for the Advancement of Learning/ McGill University
    Inventors: Warren GROSS, Shie MANNOR, Saeed SHARIFI TEHRANI
  • Publication number: 20080077839
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.
    Type: Application
    Filed: September 21, 2007
    Publication date: March 27, 2008
    Applicant: McGill University
    Inventors: Warren Gross, Shie Mannor