Patents by Inventor Warren K Gladden

Warren K Gladden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thermal monitoring and management of integrated circuits
    Patent number: 7973544
    Abstract: The invention, in one aspect, provides a semiconductor device (100), including transistors (105), dielectric layers (115, 120) located over the transistors (105), interconnects (122) formed within the dielectric layers (115, 120), and a test structure (130) located adjacent a hot-spot (125) of the semiconductor device (100) and configured to monitor a real-time operational parameter of at least one of the transistors (105) or interconnects (122).
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: July 5, 2011
    Assignee: Agere Systems Inc.
    Inventors: Vance D. Archer, III, Daniel P. Chesire, Warren K. Gladden, Seung H. Kang, Taeho Kook, Sailesh M. Merchant, Vivian Ryan
  • THERMAL MONITORING AND MANAGEMENT OF INTEGRATED CIRCUITS
    Publication number: 20100045326
    Abstract: The invention, in one aspect, provides a semiconductor device (100), including transistors (105), dielectric layers (115, 120) located over the transistors (105), interconnects (122) formed within the dielectric layers (115, 120), and a test structure (130) located adjacent a hot-spot (125) of the semiconductor device (100) and configured to monitor a real-time operational parameter of at least one of the transistors (105) or interconnects (122).
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Applicant: Agere Systems Inc.
    Inventors: Vance D. Archer, III, Daniel P. Chesire, Warren K. Gladden, Seung H. Kang, Taeho Kook, Sailesh M. Merchant, Vivian Ryan
  • Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink
    Patent number: 7429502
    Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: September 30, 2008
    Assignee: Agere Systems, Inc.
    Inventors: Vance D. Archer, III, Kouros Azimi, Daniel Patrick Chesire, Warren K Gladden, Seung H. Kang, Taeho Kook, Sailesh M. Merchant, Vivian Ryan
  • Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink
    Patent number: 7327029
    Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: February 5, 2008
    Assignee: Agere Systems, Inc.
    Inventors: Vance D. Archer, III, Kouros Azimi, Daniel Patrick Chesire, Warren K Gladden, Seung H. Kang, Taeho Kook, Sailesh M. Merchant, Vivian Ryan