Patents by Inventor Warren L. Boyer

Warren L. Boyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices with through silicon vias and package-level configurability
    Patent number: 11056467
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer
  • Semiconductor devices with package-level configurability
    Patent number: 10867991
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first contact pad, and the substrate is electrically isolated from the second contact pad.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer, Jeffrey P. Wright
  • Semiconductor devices with post-probe configurability
    Patent number: 10811372
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.
    Type: Grant
    Filed: May 18, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James E. Davis, Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer
  • SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY
    Publication number: 20200212032
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first contact pad, and the substrate is electrically isolated from the second contact pad.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 2, 2020
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer, Jeffrey P. Wright
  • SEMICONDUCTOR DEVICES WITH THROUGH SILICON VIAS AND PACKAGE-LEVEL CONFIGURABILITY
    Publication number: 20200035650
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer
  • Semiconductor devices with through silicon vias and package-level configurability
    Patent number: 10483241
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer
  • SEMICONDUCTOR DEVICES WITH POST-PROBE CONFIGURABILITY
    Publication number: 20190273052
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.
    Type: Application
    Filed: May 18, 2019
    Publication date: September 5, 2019
    Inventors: James E. Davis, Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer
  • Semiconductor devices with post-probe configurability
    Patent number: 10403585
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: James E. Davis, Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer
  • SEMICONDUCTOR DEVICES WITH POST-PROBE CONFIGURABILITY
    Publication number: 20190148314
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.
    Type: Application
    Filed: September 21, 2018
    Publication date: May 16, 2019
    Inventors: James E. Davis, Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer
  • Semiconductor devices with post-probe configurability
    Patent number: 10283462
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventors: James E. Davis, Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer