Abstract: A controller having dedicated fuser circuitry and a processor for controlling the fuser heating element. The dedicated fuser circuitry interconnects an input voltage source to the processor through a low voltage power supply to provide a reference signal and a sample DC voltage signal representative of the input voltage source. The processor provides a digital signal to activate a triac connected to the fuser heating element. The triac, selectively gates the input voltage source across the heating element. A plurality of ranges of digital signals and a plurality of corresponding triac activation rates are provided for variations in input voltage. A digital signal related to a particular value of the input voltage source lies within one of the plurality of ranges determining the particular activation rate of the triac.

Abstract: In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof.

Abstract: In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus.

Abstract: Disclosed are methods and apparatus for multi-way program branching in a digital computer based on the contents of a data register. This is accomplished by loading any data field of interest into a data register and using the output lines as address lines to a plurality of read-only memory devices. Each device contains a set of random memory addresses. Logic circuits under program control select and enable one device, thereby producing one address. Finally, circuits under program control force a program branch to the location address produced. Thus, by programming the read-only memory devices and the computer appropriately, a plurality of sets of data fields are associated with and result in branches to a plurality of sets of locations, thereby giving the programmer the general capability of branching to any one of the plurality of locations within one instruction execution cycle based on the interrogation of any one data word.

Abstract: Circuits for the improved operation of microprogrammable computers are described. This improvement is accomplished by providing a set of read-only memory devices for storing the micro-code for all combinations of arithmetic logic unit function, carry bit and file register address than can be specified by an instruction word executed from Main Memory. In a universal microprogram designed to execute that family of Main Memory instructions that differ only in the functions specified above, the instruction word is used to address the read-only memory devices, the micro-code output of which is used to control the file, carry in bit and arithmetic logic unit. Through the use of these circuits a family of instructions may be executed by a single microprogram and at no increase in execution time over that required for the execution of a microprogram dedicated to a single instruction.

Abstract: A Read-Only Memory device in the CPU of a microprogrammable computer contains a diagnostic program suitable for self-testing the computer. A microprogram for loading this diagnostic program from the Read-Only Memory device into Main Memory is contained in the Control Memory of the CPU. When required, the diagnostic program is loaded into Main Memory and executed thus allowing for the testing of a computer without the need of operational peripherals.