Abstract: An electromagnetic baffle arrangement includes a lid (22) having a trough or air gap (30) in the side walls of each cavity (23) of lid (22). Conductive strips (28) are applied to a layer of printed circuit board (26) and each of the legs (31) of lid (22). Optionally, to eliminate circulation of electromagnetic signals within air gap (30) a grounded bolt (32) may be inserted aperiodically.

Abstract: A resonator circuit (10) has a pair of varactor diodes (13, 14), a capacitor (15), and a transformer (20) coupled in parallel with the capacitor and varactor diodes. Further, in order to provide a high frequency output an impedance inverter network (35, 36) is coupled to the transformer.

Abstract: A dielectric resonator oscillator (DRO) (200, FIG. 2; 600, FIG. 6; 900, FIG. 9) includes a dielectric resonator (202, 602, 902) that is held in a fixed position with respect to the housing lid (206, 606, 906). In one embodiment, the resonator is attached to the housing lid using one or more support legs (208). In another embodiment, the resonator is attached to the housing lid using a ring structure (608). In still another embodiment, the resonator is attached to the lid and housing (904) using a lid tuner (914) and lid pedestal (908), and a housing tuner (915) and housing pedestal (909). Resonator positioning within the DRO cavity (222, 622, 922) is simplified by accurately aligning and attaching the support structure to the resonator.

Abstract: A power amplifier core (40) for amplifying RF signals is provided. The power amplifier core (40) includes a first string of FET cells (46) for amplifying the RF signal. The FET cell string includes at least two FET cells (46) connected in series with an output port (48) of the amplifier core. A bias network (44) coupled between an amplifier core input port (42) and the FET cells (46) couples the RF signal to the FET cells (46). The bias network (44) includes a bias capacitor (50) and a resistor network. The bias capacitor (50) is coupled to the input port (42) for AC coupling the RF signal to an associated FET cell (46) in the FET cell string. The resistor network is coupled from the bias capacitor (50) to the associated FET cell (46) for providing a DC bias to the associated FET cell (46).

Abstract: A two-dimensional FET array (102) within a Q-band power amplifier module is presented. Array (102) has a plurality of substantially identical one-dimensional FET arrays (106) substantially centered upon a primary axis (130) of two-dimensional array (106) substantially perpendicular to a propagation axis (110) of module (100). Each one-dimensional array (106) is formed of a plurality of FETs (128) substantially centered along a FET axis (134) substantially parallel to propagation axis (110). Each one-dimensional array (106) is proximate and coupled to each of an input bus (136) and an output bus (138), both oriented substantially parallel to propagation axis (110).

Abstract: An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).

Abstract: A method and apparatus for a probeable substrate substitute for a calibration standard and test fixture. The probestrate includes a dielectric substrate having first and second dielectric substrate surfaces and at least one conductive via hole through the dielectric substrate from the first dielectric substrate surface to the second dielectric substrate surface. A first metalized layer is in contact with the first dielectric substrate surface and the at least one conductive via hole. A second metalized layer is in contact with a first portion of the second dielectric substrate surface and with the at least one conductive via hole. The first and second test ports contact a second portion of the second dielectric substrate surface. An electronic device can be connected to the first and second test ports with bond wires for characterization via contact of the first and second test ports with standard test station equipment.

Abstract: An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).

Abstract: A mixer separates IF components IF1, IF2 of the same frequency which are images of different frequency RF signals RF1, RF2 beating with a given LO signal. The LO signal is applied to a FET active power divider and applied to the drains of a pair of balanced FET mixing elements. The FETs for the active power divider are built from the same device structure as the FETs for the mixing elements sharing drain nodes. The RF signals are passed through a quadrature phase shifter and applied to the gates of the FET mixing elements. The mixed signals appear at the drains of FET mixing elements are applied to opposing ports of a second quadrature hybrid at whose output ports the separated IF output signals IF1, IF2 appear.

Abstract: A high isolation microwave module includes a housing floor with mounting surfaces for placing microwave components and housing walls ending in housing wall ends coupled to and projecting from the housing floor. A lid including a lid plate and lid walls ending in lid wall ends projects from the lid plate. The lid walls extend toward the housing floor and the plurality of housing walls extend toward the lid plate but neither the lid wall ends nor the housing wall ends are coupled to the housing floor or lid plate, respectively. A plurality of cavities exist between the adjacent lid walls between the housing and the lid plate and a plurality of irises exist between immediately adjacent housing walls and corresponding lid walls. The irises and cavities act as a multi-section high pass filter to provide attenuation to a microwave signal passing through the module.

Abstract: A signal mixing apparatus comprising first and second four port signal splitting/combining networks having no relative phase shift between three ports and 180.degree. of phase shift between the remaining ports, coupled to a four port mixer element. The mixer element has two ports coupled to the first signal splitter/combiner network and having another two ports coupled to the second splitter/combiner, RF and LO signals input to the first splitter/combiner do not appear at the IF output from the second splitter/combiner or vice versa. The RF/IF signals cancel and the LO signal is trapped by a resonant circuit within the mixer. The RF and IF frequency bands may overlap.

Abstract: An apparatus for mixing electrical signals including in combination: first signal splitting means having a radio frequency (RF) port and first, second, third and fourth signal ports, second signal splitting means having a local oscillator (LO) port and first, second, third and fourth signal ports, intermediate frequency (IF) port, and mixer element means, the mixer element means coupled to the first, second, third, and fourth signal ports of the first and second signal splitting means and coupled to the intermediate frequency port means, for mixing two of the RF, IF, and LO signals to produce the remaining signal.

Abstract: A N-stage differential distributed amplifier arrangement. The differential distributed amplifier arrangement includes a parallel connection of N-differential amplifiers. The inputs to the amplifiers are delayed so that the same input is received by each amplifier in sequence at a slightly later time than the preceding amplifier. The outputs of each amplifier are also delayed so that the output of the previous amplifier is added to the output of the next sequential amplifier. Thereby the output is an amplified version of the input. By appropriate grounding of inputs or outputs the differential distributed amplifier arrangement may convert from balanced signals to single-ended signals, from single-ended signals to balanced signals or from two inputs to two outputs.

Abstract: A logarithmic amplifier includes amplifier stages having an input transmission line and first and second output transmission lines. The input and output transmission line are coupled by multiple amplifier elements distributed along the transmission lines. One output transmission line forms a high gain low compression path and the other a low gain high compression path. The output transmission lines of each stage are coupled to a combiner from whence the logarithmically amplified output signal is obtained. The logarithmic amplifier stages are readily constructed in MMIC form and multiple stages may be easily cascaded to provide a very large dynamic range.

Abstract: A method for creating a four-port quadrature coupler suitable for monolithic implementation which involves connecting two ports of a balun, suitable itself for implementation in monolithic microwave integrated circuits, to two separate phasing networks. A device exhibiting the proper four-port quadrature coupler characteristics within a MMIC structure results, with wide bandwidth exceeding one octave.

Abstract: High and low pass filters are coupled to a power divider to create a multi-phase hybrid. The high and low pass filters, and the power divider, are all lumped element for compatibility with MMIC circuitry. The power divider may output, to the high and low pass filters, signals having equal or unequal amplitudes. Similiarly, the high and low pass filters may output signals having equal or unequal phases.

Abstract: A FET structure has first and second active areas separated by an inactive area with a gate bus located thereon. Gate fingers extend from the gate bus between source and drain contacts on the active areas. Bridges extend over the gate bus and interconnect the source contacts.

Abstract: A broadband 180 degree hybrid having lumped or semi-lumped elements is comprised of a network of low and high pass filters. A 180 degree phase differential is obtained by splitting an input signal from a first input. A first portion of the split signal is passed through a low pass filter and a second portion is passed through a high pass filter. The phase differential is maintained at 180 degrees. A zero (0) degree phase differential is obtained by splitting an input signal from a second input and passing both portions through a pair of low pass filters or through a pair of high pass filters.

Abstract: A passive 180 degree MMIC (monolithic microwave integrated circuit) hybrid is developed which yields broad band widths, decreases the circuit surface area to increase production yield, and is compatible with GaAs (gallium arsenide) media used in MMIC circuits. The passive 180 degree MMIC hybrid comprises a in-phase combiner coupled to a delay transmission line through a plurality of adjusting capacitors. The coupling points of the in-phase combiner and the delay transmission line are further coupled to respective 180 degree hybrid outputs. A 0/180 input is coupled in common to the delay transmission line. The 90 degree hybrid comprises a plurality of transmission lines coupled to a 0/0 input of the 180 degree hybrid.

Abstract: A 90 degree hybrid is contemplated having three parallel signal paths, one of the signal paths is a central signal path which provides direct impedence to ground. The other two signal paths are capacitively coupled to the central signal path to provide a second impedence. Each signal path incorporates at least one inductor coupled in series along each of the signal paths. The signal paths are capacitively coupled to each other at each end of the inductors. To increase the bandwidth, additional hybrids are coupled in series, with each hybrid forming a section of the broadband hybrid.