Patents by Inventor Warren L. Ziegenfus

Warren L. Ziegenfus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programmable logic devices with integrated standard-cell logic blocks
    Patent number: 6975137
    Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: December 13, 2005
    Assignee: Lattice Semiconductor Corporation
    Inventors: John A. Schadt, William B. Andrews, Zheng Chen, Anthony K. Myers, David A. Rhein, Warren L. Ziegenfus, Fulong Zhang, Ming Hui Ding, Larry R. Fenstermaker
  • Programmable logic devices with integrated standard-cell logic blocks
    Patent number: 6870395
    Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: March 22, 2005
    Assignee: Lattice Semiconductor Corporation
    Inventors: John A. Schadt, William B. Andrews, Zheng Chen, Anthony K. Myers, David A. Rhein, Warren L. Ziegenfus, Fulong Zhang, Ming Hui Ding, Larry R. Fenstermaker
  • Programmable logic devices with integrated standard-cell logic blocks
    Publication number: 20040183564
    Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.
    Type: Application
    Filed: March 18, 2003
    Publication date: September 23, 2004
    Applicant: Lattice Semiconductor Corporation, a Delaware corporation
    Inventors: John A. Schadt, William B. Andrews, Zheng Chen, Anthony K. Myers, David A. Rhein, Warren L. Ziegenfus, Fulong Zhang, Ming Hui Ding, Larry R. Fenstermaker
  • Integrated circuit base transistor structure and associated programmable cell library
    Patent number: 6781170
    Abstract: A base transistor structure and associated programmable cell library compatible with standard cell computer-aided design (CAD) tools are disclosed. In an illustrative embodiment of the invention, the base transistor structure is symmetric about one or more axes, and extends only a single grid of a standard cell CAD tool in width. The base transistor structure is advantageously configured in a manner that permits the utilization of gate isolation to separate active transistors in adjacent base transistor structures. The base transistor structure can be used to implement a programmable cell technology that is fully compatible with standard cell CAD tools.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: August 24, 2004
    Assignee: Lattice Semiconductor Corporation
    Inventors: Stephen R. Cebenko, David A. Rhein, John A. Schadt, Brian W. Yeager, Warren L. Ziegenfus
  • Integrated circuit base transistor structure and associated programmable cell library
    Publication number: 20020163048
    Abstract: A base transistor structure and associated programmable cell library compatible with standard cell computer-aided design (CAD) tools are disclosed. In an illustrative embodiment of the invention, the base transistor structure is symmetric about one or more axes, and extends only a single grid of a standard cell CAD tool in width. The base transistor structure is advantageously configured in a manner that permits the utilization of gate isolation to separate active transistors in adjacent base transistor structures. The base transistor structure can be used to implement a programmable cell technology that is fully compatible with standard cell CAD tools.
    Type: Application
    Filed: February 14, 2002
    Publication date: November 7, 2002
    Inventors: Stephen R. Cebenko, David A. Rhein, John A. Schadt, Brian W. Yeager, Warren L. Ziegenfus