Abstract: A discharge circuit for rapidly discharging the word lines of random access memories to thereby prevent erroneous reading from or writing into the memory during periods when the word lines are in a mid-state transition between selected and deselected voltage levels. Each discharge circuit associated with the memory word lines includes a transistor that is conductive only when a full select voltage level is applied to the word line and which controls conduction of a second multi-collector transistor coupled between top and bottom lines of a word line pair and a current source to discharge the word line pair during the mid-state transition period and to thus increase the speed capabilities of the memory.

Abstract: A method and circuitry (5) for enhancing the reproducibility and reliability of circuitry for reading a memory array (10a, 10b, 10a', 10b') provides a dynamically generated reference voltage for the sensing circuitry. The invention senses the highest word line voltage and communicates a voltage derived therefrom to the sensing circuitry (26, 27, 28, 29; 26', 27', 28', 29'; 32, 33) to provide a reference voltage. A voltage clamp (62) is coupled to the circuitry for communicating the highest word line voltage (50) to prevent the reference voltge from following the word line too low during transitions. The invention is rendered compatible with the existing write circuitry associated with the memory array (10a, 10b, 10a', 10b') by the provision of disabling circuitry (65) coupled to the communicating circuitry (55, 57) and to the clamp (62).

Abstract: Circuitry responsive to a memory chip de-select signal for very rapidly decoupling the memory from its peripheral circuits and for turning off all unnecessary power and, upon occurrence of a chip select signal, for rapidly restoring power and then recoupling the memory after a preselected word line voltage is reached and all transients have subsided, thereby preventing erroneous writing and reading during chip select and de-select.