Abstract: An electronic device display may have pixels formed from crystalline semiconductor light-emitting diode dies, organic light-emitting diodes, or other pixel structures. The pixels may be formed on a display panel substrate. A display panel may extend continuously across the display or multiple display panels may be tiled in two dimensions to cover a larger display area. Interconnect substrates may have outwardly facing contacts that are electrically shorted to corresponding inwardly facing contacts such as inwardly facing metal pillars associated with the display panels. The interconnect substrates may be supported by glass layers. Integrated circuits may be embedded in the display panels and/or in the interconnect substrates. A display may have an active area with pixels that includes non-spline pixels in a non-spline display portion located above a straight edge of the display and spline pixel in a spline display portion located above a curved edge of the display.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: An electronic device may have a housing with a display. The display may be overlapped by an image transport layer such as a coherent fiber bundle or layer of Anderson localization material. The image transport layer may have an input surface that receives an image from the display and a corresponding output surface to which the image is transported. The input surface and output surface may have different shapes. A wristwatch device may, as an example, have a rectangular or hexagonal input surface and may have an output surface such as a rectangular output surface with rounded corners or a circular output surface. A region of the output surface may have compound curvature. A portion of the image transport layer may protrude laterally over an inactive portion of the display.

Abstract: This disclosure is directed towards systems and methods of power saving in electronic displays based on changing clock signal frequencies supplied to the gate-in-panel (GIP) circuitry during extended blanking modes of the electronic display. The display driver circuitry of the display may reduce and/or halt clock signal frequencies sent to GIP circuitry in the display, to reduce power output during extended blanking modes of the electronic display.

Abstract: To reduce the amount of space occupied in the inactive area of a display by gate driver circuitry, at least a portion of the gate driver circuitry may be positioned in the active area of the display. To accommodate the gate driver circuitry, emissive sub-pixels may be laterally shifted relative to corresponding thin-film transistor sub-pixels. This allows for the thin-film transistor sub-pixels to be grouped adjacent to the central area of the active area, leaving room along an edge of the active area to accommodate one or more additional display components such as gate driver circuitry or fanout portions of data lines.

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Abstract: A light emitter that operates through a display may cause display artifacts, even when the light emitter operates using non-visible wavelengths. Display artifacts caused by a light emitter that operates through a display may be referred to as emitter artifacts. To mitigate emitter artifacts, operating conditions for a display frame may be used to determine an optimal firing time for the light emitter during that display frame. The operating conditions used to determine the optimal firing time may include emitter operating conditions, display content statistics, display brightness, temperature, and refresh rate. Operating conditions from one or more previous frames may be stored in a frame buffer and may be used to help determine the optimal firing time for the light emitter during a display frame. Pixel values for the display may be modified to mitigate emitter artifacts.

Abstract: An electronic device may include a display having display pixels formed in an active area of the display. The display further includes display driver circuitry for driving gate lines that are routed across the display. A hole such as a through hole, optical window, or other inactive region may be formed within the active area of the display. Multiple gate lines carrying the same signal may be merged together prior to being routed around the hole to help minimize the routing line congestion around the border of the hole. Dummy circuits may be coupled to the merged segment portion to help increase the parasitic loading on the merged segments. The hole may have a tapered shape to help maximize the size of the active area. The hole may have an asymmetric shape to accommodate multiple sub-display sensor components.

Abstract: An electronic device may include a display and an optical sensor formed underneath the display. The electronic device may include a plurality of transparent windows that overlap the optical sensor. The resolution of the display panel may be reduced in some areas due to the presence of the transparent windows. To mitigate diffraction artifacts, a first sensor (13-1) may sense light through a first pixel removal region having transparent windows arranged according to a first pattern. A second sensor (13-2) may sense light through a second pixel removal region having transparent windows arranged according to a second pattern that is different than the first pattern. The first and second patterns of the transparent windows may result in the first and second sensors having different diffraction artifacts. Therefore, an image from the first sensor may be corrected for diffraction artifacts based on an image from the second sensor.

Abstract: An electronic device may include a display having display pixels formed in an active area of the display. The display further includes display driver circuitry for driving gate lines that are routed across the display. A hole such as a through hole, optical window, or other inactive region may be formed within the active area of the display. Multiple gate lines carrying the same signal may be merged together prior to being routed around the hole to help minimize the routing line congestion around the border of the hole. Dummy circuits may be coupled to the merged segment portion to help increase the parasitic loading on the merged segments. The hole may have a tapered shape to help maximize the size of the active area. The hole may have an asymmetric shape to accommodate multiple sub-display sensor components.

Abstract: Touch electrode architecture techniques can be used to reduce or eliminate metal mesh within the one or more high-transmittance regions of a touch screen including one or more high-transmittance regions. In some examples, one or more optical devices can be integrated with a touch screen such that light associated with the one or more optical devices passes through one or more layers of the touch screen. In some such examples, to avoid degrading performance of the optical devices, one or more high-transmittance regions can be used. Additionally or alternatively, in some examples, the high-transmittance can be achieved using touch electrode architecture techniques that use transparent or semi-transparent materials instead of opaque metal mesh within the high-transmittance regions.

Abstract: An electronic device may have a display with an active area configured to display images and an inactive area that is free of pixels and that does not display images. Touch sensor sense lines may have portions located in the active area and portions located in the inactive area. The active and inactive areas may be characterized by respective reflectivity values. To match the reflectivities of the active and inactive areas and thereby avoid undesired visually distinguishable differences in the appearances of these areas, the touch sensor circuitry in the inactive areas may be configured to match the reflectivity values of the active and inactive areas. Sense line portions in the inactive area may have metal traces of enhanced reflectivity and/or uneven surface topology to enhance ambient light reflections through a circular polarizer that overlaps the active and inactive areas.

Abstract: A display may have both a full pixel density region and a pixel removal region with a plurality of high-transmittance areas that overlap an optical sensor. Each high-transmittance area may be devoid of thin-film transistors and other display components. To improve transmission while maintaining satisfactory touch sensing performance, one or more segments of the touch sensor metal in the pixel removal region may have a reduced width relative to the touch sensor metal in the full pixel density region and/or one or more segments of the touch sensor metal in the pixel removal region may be omitted relative to the touch sensor metal in the full pixel density region. To mitigate a different appearance between the pixel removal region and the full pixel density region at off-axis viewing angles, the position of the touch sensor metal in the pixel removal region may be tuned.

Abstract: A display may have both a full pixel density region and a pixel removal region with a plurality of high-transmittance areas that overlap an optical sensor. Each high-transmittance area may be devoid of thin-film transistors and other display components. To improve transmission while maintaining satisfactory touch sensing performance, one or more segments of the touch sensor metal in the pixel removal region may have a reduced width relative to the touch sensor metal in the full pixel density region and/or one or more segments of the touch sensor metal in the pixel removal region may be omitted relative to the touch sensor metal in the full pixel density region. To mitigate a different appearance between the pixel removal region and the full pixel density region at off-axis viewing angles, the position of the touch sensor metal in the pixel removal region may be tuned.

Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

Abstract: An organic light-emitting diode display may have thin-film transistor circuitry formed on a substrate. The display and substrate may have rounded corners. A pixel definition layer may be formed on the thin-film transistor circuitry. Openings in the pixel definition layer may be provided with emissive material overlapping respective anodes for organic light-emitting diodes. A cathode layer may cover the array of pixels. A ground power supply path may be used to distribute a ground voltage to the cathode layer. The ground power supply path may be formed from a metal layer that is shorted to the cathode layer using portions of a metal layer that forms anodes for the diodes, may be formed from a mesh shaped metal pattern, may have L-shaped path segments, may include laser-deposited metal on the cathode layer, and may have other structures that facilitate distribution of the ground power supply.

Abstract: To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

Abstract: An organic light-emitting diode display may have thin-film transistor circuitry formed on a substrate. The display and substrate may have rounded corners. A pixel definition layer may be formed on the thin-film transistor circuitry. Openings in the pixel definition layer may be provided with emissive material overlapping respective anodes for organic light-emitting diodes. A cathode layer may cover the array of pixels. A ground power supply path may be used to distribute a ground voltage to the cathode layer. The ground power supply path may be formed from a metal layer that is shorted to the cathode layer using portions of a metal layer that forms anodes for the diodes, may be formed from a mesh shaped metal pattern, may have L-shaped path segments, may include laser-deposited metal on the cathode layer, and may have other structures that facilitate distribution of the ground power supply.