Patents by Inventor Warren W. Flack

Warren W. Flack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8796053
    Abstract: Photolithographic methods of forming a roughened surface for an LED to improve LED light emission efficiency are disclosed. The methods include photolithographically imaging a phase-shift mask pattern onto a photoresist layer of a substrate to form therein a periodic array of photoresist features. The roughened substrate surface is created by processing the exposed photoresist layer to form a periodic array of substrate posts in the substrate surface. A p-n junction multilayer structure is then formed atop the roughened substrate surface to form the LED. The periodic array of substrate posts serve as scatter sites that improve the LED light emission efficiency as compared to the LED having no roughened substrate surface. The use of the phase-shift mask enables the use of affordable photolithographic imaging at a depth of focus suitable for non-flat LED substrates while also providing the needed resolution to form the substrate posts.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: August 5, 2014
    Assignee: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Robert L. Hsieh, Warren W. Flack
  • Patent number: 8781213
    Abstract: An alignment system for aligning a wafer when lithographically fabricating LEDs having an LED wavelength ?LED is disclosed. The system includes the wafer. The wafer has a roughened alignment mark with a root-mean-square (RMS) surface roughness ?S. The system has a lens configured to superimpose an image of the reticle alignment mark with an image of the roughened alignment mark. The roughened alignment marked image is formed with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. An image sensor detects the superimposed image. An image processing unit processes the detected superimposed image to measure an alignment offset between the wafer and the reticle.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Ultratech, Inc.
    Inventors: Robert L. Hsieh, Khiem Nguyen, Warren W. Flack, Andrew M. Hawryluk
  • Patent number: 8323857
    Abstract: A phase-shift mask having a checkerboard array and a surrounding sub-resolution assist phase pattern. The checkerboard array comprises alternating phase-shift regions R that have a relative phase difference of 180 degrees. The sub-resolution assist phase regions R? reside adjacent corresponding phase-shift regions R and have a relative phase difference of 180 degrees thereto. The sub-resolution assist phase regions R? are configured to mitigate undesirable edge effects when photolithographically forming photoresist features. Method of forming LEDs using the phase-shift mask are also disclosed.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: December 4, 2012
    Assignee: Ultratech, Inc.
    Inventors: Robert L. Hsieh, Warren W. Flack
  • Publication number: 20120153323
    Abstract: Photolithographic methods of forming a roughened surface for an LED to improve LED light emission efficiency are disclosed. The methods include photolithographically imaging a phase-shift mask pattern onto a photoresist layer of a substrate to form therein a periodic array of photoresist features. The roughened substrate surface is created by processing the exposed photoresist layer to form a periodic array of substrate posts in the substrate surface. A p-n junction multilayer structure is then formed atop the roughened substrate surface to form the LED. The periodic array of substrate posts serve as scatter sites that improve the LED light emission efficiency as compared to the LED having no roughened substrate surface. The use of the phase-shift mask enables the use of affordable photolithographic imaging at a depth of focus suitable for non-flat LED substrates while also providing the needed resolution to form the substrate posts.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Inventors: Andrew M. Hawryluk, Robert L. Hsieh, Warren W. Flack
  • Publication number: 20120156814
    Abstract: A phase-shift mask having a checkerboard array and a surrounding sub-resolution assist phase pattern. The checkerboard array comprises alternating phase-shift regions R that have a relative phase difference of 180 degrees. The sub-resolution assist phase regions R? reside adjacent corresponding phase-shift regions R and have a relative phase difference of 180 degrees thereto. The sub-resolution assist phase regions R? are configured to mitigate undesirable edge effects when photolithographically forming photoresist features. Method of forming LEDs using the phase-shift mask are also disclosed.
    Type: Application
    Filed: April 25, 2011
    Publication date: June 21, 2012
    Inventors: Robert L. Hsieh, Warren W. Flack
  • Publication number: 20120062726
    Abstract: An alignment system for aligning a wafer when lithographically fabricating LEDs having an LED wavelength ?LED is disclosed. The system includes the wafer. The wafer has a roughened alignment mark with a root-mean-square (RMS) surface roughness ?S. The system has a lens configured to superimpose an image of the reticle alignment mark with an image of the roughened alignment mark. The roughened alignment marked image is formed with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. An image sensor detects the superimposed image. An image processing unit processes the detected superimposed image to measure an alignment offset between the wafer and the reticle.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 15, 2012
    Inventors: Robert L. Hsieh, Khiem Nguyen, Warren W. Flack, Andrew M. Hawryluk
  • Patent number: 8088633
    Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness ?S. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: January 3, 2012
    Assignee: Ultratech, Inc.
    Inventors: Robert L. Hsieh, Khiem Nguyen, Warren W. Flack, Andrew M. Hawryluk
  • Publication number: 20110129948
    Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness ?S. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength ?A that is in the range from about 2 ?S to about 8 ?S. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 2, 2011
    Inventors: Robert L. Hsieh, Khiem Nguyen, Warren W. Flack, Andrew M. Hawryluk