Abstract: A fuel injector for a gas turbine engine may include a pilot assembly extending along a longitudinal axis. The pilot assembly may be configured to direct a pilot fuel-air mixture to a combustor of the gas turbine engine. The fuel injector may also include a rich catalyst module circumferentially disposed about the pilot assembly. The catalyst module may be configured to simultaneously direct a stream of compressed air and a stream of first fuel-air mixture therethrough without intermixing. The fuel injector may also include a post mix zone disposed downstream of the catalyst module. The post mix zone may be configured to mix the compressed air and the first fuel air mixture to create a main fuel-air mixture. The fuel injector may further include an air swirler disposed downstream of the post mix zone. The air swirler may be configured to direct the main fuel-air mixture to the combustor without intermixing with the pilot fuel-air mixture.

Abstract: A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.

Abstract: An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

Abstract: An linear equalizer system for a transmission channel includes an active inductor with a tunable inductance and quality factor. The active inductor includes a transconducting element. A current steering digital to analog converter controls the flow of a bias current through the transconducting element to tune the active inductor.

Abstract: A method for determining the value of at least one capacitance required to be placed in a conductive path on a printed circuit board is disclosed. The method includes preparing a desired signal spectrum for the conductive path, preparing an actual signal spectrum for the conductive path, and then comparing the actual signal spectrum against the desired signal spectrum to determine where any out of tolerance conditions exist. If the actual signal spectrum is in amplitude versus time form, the method further includes performing, for each time having a voltage which is higher than the maximum voltage allowed on the conductive path, a fourier transform on the amplitude versus time data.

Abstract: A 5 volt tolerant I/O buffer circuit is coupled to a power supply terminal of a predetermined power supply voltage, for driving an I/O pad to a logic state depending on an input signal and an output enable signal. The I/O buffer circuit minimizes current flow into the power supply terminal when the pad is coupled to a voltage greater than the predetermined power supply voltage. A driver transistor of a first type is formed within a diffusion well and is coupled to the predetermined power supply voltage and to the pad. First and second terminals of a protection transistor are coupled to respective ones of the predetermined power supply voltage and the diffusion well. Circuitry is provided for, when the output enable signal is active, turning on the protection transistor so as to couple the predetermined power supply voltage to the diffusion well, regardless of a voltage level of the pad. A single protection transistor is sufficient to prevent current leakage through the parasitic PN diode.

Abstract: A output driving circuit having an output driving element, an overshoot protection mechanism, and an undershoot protection mechanism. When the overshoot protection mechanism senses an overshoot voltage at the output terminal of the output driving element, it raises the voltage at the control terminal of the output driving element. This serves to maintain the voltage between the output terminal and the control terminal of the output driving element within a safe range, thereby preventing overstress or damage to the element. When the undershoot protection mechanism senses an undershoot voltage at the output terminal of the output driving element, it lowers the voltage at the control terminal of the output driving element. This serves to maintain the voltage between the output terminal and the control terminal of the output driving element within a safe range, which in turn prevents overstress and damage to the element.

Abstract: A mixed voltage compatible buffer having reduced power consumption is provided. One embodiment of the buffer according to the present invention comprises: a data input configured to receive an output data signal; a data interface configured to couple with a pad interconnect; an output driver coupled with said data interface and being configured to apply the output data signal thereto; and a data controller intermediate said data input and said output driver, said data controller being configured to apply a plurality of control signals of substantially equal voltage to said output driver to control the operation thereof responsive to the output data signal received via said data input. The present invention also provides for a method of transferring data within the buffer.