Abstract: Aspects of a prefetch module for high throughput memory transfers is described. Data stored in a row buffer of a memory device can be quickly transferred over a serial link to a prefetch buffer. In one example, a number of respective serial links can be used to transfer the data stored in several row buffers of respective memory devices to the prefetch buffer. In the prefetch buffer, all the data from the memory devices is stored in a data cache. Once the data is cached at the prefetch buffer, a memory controller can access it more quickly in any suitable way. As compared to conventional approaches, the embodiments can be relied upon to avoid a significant amount of latency in memory read and write operations with memory modules.

Abstract: An error injection system of a built-in self-repairable memory system renders the redundant spare columns of the repairable memory accessible to built-in self-test (BIST) read and write operations. To this end, the error injection system selectively injects fault data at one or more locations of the main memory during a BIST sequence, causing the BIST controller to issue a repair instruction that allocates one or more spare columns as replacement memory areas for the presumed faulty main memory locations. Thereafter, BIST read/write operations directed to the main memory locations will be performed on the allocated spare columns, thereby allowing the spare columns to be validated as part of the BIST. Injection of fault data to the main memory locations in this manner can also facilitate validation of the built-in self-repair logic by verifying the repair instruction codes that are generated in response to the injected faults.

Abstract: An error injection system of a built-in self-repairable memory system renders the redundant spare columns of the repairable memory accessible to built-in self-test (BIST) read and write operations. To this end, the error injection system selectively injects fault data at one or more locations of the main memory during a BIST sequence, causing the BIST controller to issue a repair instruction that allocates one or more spare columns as replacement memory areas for the presumed faulty main memory locations. Thereafter, BIST read/write operations directed to the main memory locations will be performed on the allocated spare columns, thereby allowing the spare columns to be validated as part of the BIST. Injection of fault data to the main memory locations in this manner can also facilitate validation of the built-in self-repair logic by verifying the repair instruction codes that are generated in response to the injected faults.

Abstract: In one embodiment a system comprises an integrated circuit, a plurality of voltage regulators; and a data bus coupled to the integrated circuit and the plurality of voltage regulators. In some embodiments the integrated circuit comprises logic to embed a timing signal on the data bus. Other embodiments may be described.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: In one embodiment a system comprises an integrated circuit, a plurality of voltage regulators; and a data bus coupled to the integrated circuit and the plurality of voltage regulators. In some embodiments the integrated circuit comprises logic to embed a timing signal on the data bus. Other embodiments may be described.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the integrated circuit, and communicate with the plurality of voltage regulators that are electrically coupled to the integrated circuit at a speed associated with the slowest one of the plurality of voltage regulators.