Patents by Inventor Wataru Arakawa

Wataru Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240148727
    Abstract: The compound of formula (1a) wherein p is 1 or 2, R1-R4 are hydrogen atom or the like, and a-d are 1 or 2, or a pharmaceutically acceptable salt thereof, which has an antitumor effect by inhibiting the binding between a MLL fusion protein that is infused with AF4, AF9, or the like, which is a representative fusion partner gene causing MLL leukemia, and menin.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: Sumitomo Pharma Co., Ltd.
    Inventors: Seiji KAMIOKA, Hitoshi BAN, Naoaki SHIMADA, Wataru HIROSE, Akihiko ARAKAWA, Kazuto YAMAZAKI, Kenjiro HIRA
  • Patent number: 11911381
    Abstract: The compound of formula (1a) wherein p is 1 or 2, R1-R4 are hydrogen atom or the like, and a-d are 1 or 2, or a pharmaceutically acceptable salt thereof, which has an antitumor effect by inhibiting the binding between a MLL fusion protein that is infused with AF4, AF9, or the like, which is a representative fusion partner gene causing MLL leukemia, and menin.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 27, 2024
    Assignee: Sumitomo Pharma Co., Ltd.
    Inventors: Seiji Kamioka, Hitoshi Ban, Naoaki Shimada, Wataru Hirose, Akihiko Arakawa, Kazuto Yamazaki, Kenjiro Hira
  • Patent number: 5483490
    Abstract: An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus.
    Type: Grant
    Filed: December 1, 1993
    Date of Patent: January 9, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Hidetoshi Iwai, Masamichi Ishihara, Kazuya Ito, Wataru Arakawa, Yoshinobu Nakagome
  • Patent number: 5410507
    Abstract: A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: April 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Shigetoshi Sakomura, Toshitsugu Takekuma, Yutaka Ito, Kazuya Ito, Wataru Arakawa, Hidetoshi Iwai, Toshiyuki Sakuta, Masamichi Ishihara
  • Patent number: 5289416
    Abstract: An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus.
    Type: Grant
    Filed: January 14, 1992
    Date of Patent: February 22, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hidetoshi Iwai, Masamichi Ishihara, Kazuya Ito, Wataru Arakawa, Yoshinobu Nakagome