Abstract: An information processor includes a memory; and a processor coupled to the memory and the processor configured to: acquire first statistical information about distribution of most significant bit position that is not a sign or least significant bit position that is not zero for each of a plurality of first fixed-point number data, the data being a computation result of the computation in the first layer; execute computation on a plurality of output data of the first layer according to a predetermined rule, in the computation in the second layer; and acquire second statistical information based on the predetermined rule and the first statistical information, and determine a bit range for limiting a bit width when a plurality of second fixed-point number data, the data being a computation result of the computation in the second layer, are stored in a register, based on the second statistical information.

Abstract: An information processor includes a memory; and a processor coupled to the memory and the processor configured to: acquire first statistical information about distribution of most significant bit position that is not a sign or least significant bit position that is not zero for each of a plurality of first fixed-point number data, the data being a computation result of the computation in the first layer; execute computation on a plurality of output data of the first layer according to a predetermined rule, in the computation in the second layer; and acquire second statistical information based on the predetermined rule and the first statistical information, and determine a bit range for limiting a bit width when a plurality of second fixed-point number data, the data being a computation result of the computation in the second layer, are stored in a register, based on the second statistical information.

Abstract: An arithmetic processing device includes an arithmetic circuit; a register storing operation output data; a statistics acquisition circuit generating, from subject data being either the operation output data or normalization subject data, a bit pattern indicating a position of a leftmost set bit for positive number or a position of a leftmost zero bit for negative number of the subject data, the leftmost bit being a bit different from a sign bit; and a statistics aggregation circuit generating either positive or negative statistical information, or both positive and negative statistical information, by separately adding up a first number at respective bit positions of the leftmost set bit indicated by the bit pattern of each of a plurality of subject data having a positive sign bit and a second number of at respective bit positions of the leftmost zero bit indicated by the bit pattern of each of a plurality of subject data having a negative sign bit.

Abstract: An encoder includes a memory and a processor coupled to the memory and configured to: divide an image to be processed among sequentially input images into a plurality of small images; encode the plurality of small images; transmit each of the small images encoded by the encoding processing unit in correspondence with information indicating a position in the image to be processed; and change a division position of the image by the image dividing unit with respect to other image followed by the image to be processed according to processing information at the time of executing the encoding.

Abstract: A transmission method executed by a transmission apparatus including a plurality of reception modules that receive packets and a plurality of transmission modules that receive the packets and transmit the packets to destinations of the packets, the transmission method includes extracting, by each of the plurality of reception modules, the amounts of data for respective priority levels of the received packets; transmitting, to one of the plurality of transmission modules, information regarding the extracted amounts of data for the respective priority levels; determining, by the one of the plurality of transmission modules, the amounts of discard data to be discarded for the plurality of respective reception modules, based on the extracted amounts of data for the respective priority levels and the amount of packet data that is able to be output; and notifying the plurality of reception modules of feedback information related to the determined amounts of discard data.

Abstract: In the encoding/decoding system, when encoding an image, the image encoding device divides the encoding-target image into several subimages, and executes the encoding on the subimages in a direction moving away from the boundary of the divided subimages. In addition, when executing the encoding process, the image encoding device transmits pixels in the vicinity of the boundary of the subimages as uncompressed data, without encoding the pixels. Furthermore, when executing an encoding process, the image encoding device changes quantizing steps that are used in the encoding in accordance with a distance from the boundary so that an amount of data greater than or equal to a predetermined value can be assigned for the vicinity of the boundary by use of smaller quantizing steps.