Abstract: An optical packet switching device causes branching of an optical packet that is input to an optical switch and detects a synchronization pattern having a predetermined number of bits from the branched optical packet. Then, the optical packet switching device calculates a synchronization point indicating a location of the synchronization pattern with respect to a detection timing and controls, in accordance with the calculated synchronization point, a delay amount of a delay element that delays an optical packet ON signal that is output to the optical switch.

Abstract: An optical packet switching apparatus includes an optical packet switching apparatus, an optical transmitting apparatus, and an optical packet receiving apparatus. The optical packet transmitting apparatus includes a packet generator for generating a packet signal by adding the routing information to a received client signal, a BIP adding unit for adding BIP to the generated packet signal, and an electrical-to-optical converter for converting the packet signal, to which the BIP has been added, into an optical packet signal so as to be sent out. The optical packet receiving apparatus includes an electrical-to-optical converter for converting the received optical packet signal into an electrical packet signal, and a BIP comparison unit for detecting the error occurrence in the packet signal, based on the BIP added to the packet signal.

Abstract: An optical packet switch device includes an optical switch control section and an optical switch section. The optical switch control section includes a synchronization pattern detecting unit which detects a frame synchronization pattern from a parallel data signal and detects a delay bit number showing that the frame synchronization pattern is stored at a position shifted by how many bits from the first bit of the parallel data signal, a header analysis unit which analyzes a header and detects an optical packet length and route information of an optical packet signal, and an output competition determining unit which determines passing/discarding of the optical packet signals competing with each other based on the optical packet length and the route information detected by the header analysis unit and delay bit number information detected by the synchronization pattern detecting unit.

Abstract: An optical packet switching apparatus includes an optical coupler, an optical switch unit, and an optical switch control unit. The optical switch control unit includes an optical-to-electrical converter, a serial/parallel converter, an arrangement detector, a rearrangement unit, a frame synchronization unit, a route detector, a control signal generator, and an adjustment unit for adjusting the timing with which to output an optical switch control signal to the optical switch unit, based on arrangement information on a frame synchronization pattern fed from the arrangement detector.

Abstract: Provided is a wavelength division multiplexing transmission apparatus that enables operation control of transponders each carrying an FBTL optical module from the monitoring control unit by the same operation control as one for the transponders each carrying an NB optical module with four wavelengths assigned. For that purpose, the wavelength division multiplexing transmission apparatus includes the transponders for converting optical signals from wideband wavelengths to narrowband wavelengths, and a monitoring control unit for controlling the transponders by instructions from an operator.

Abstract: A reference-clock selection circuit for a communication interface apparatus in which signals are input via a plurality of channels includes an insertion-stuff-bit-amount monitoring unit that monitors an insertion stuff bit amount to be inserted in the signal; a channel detecting unit that detects a channel where the insertion stuff bit amount inserted in the signal matches an insertion stuff bit amount of a reference signal from a reference clock oscillator; and a reference-clock selecting unit that selects the detected channel as a reference clock for network synchronization of a connected network.

Abstract: A transmission apparatus has a main signal processing device, a monitor control part and an intermediating part to intermediate addresses and data between the monitor control part and the main signal processing device. The transmission apparatus further has a first switching part to selectively supply the address or the address and the data output from the intermediating part to the main signal processing device in the normal operation mode, and to selectively supply the address or the address and the data output from the monitor control part to the main signal processing device in the debug mode, and a second selecting part to selectively supply the data output from the intermediating part to the monitor control part in the normal operation mode, and to selectively supply the data output from the main signal processing device to the monitor control part in the debug mode.

Abstract: There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynamically sets a frequency-dividing ratio based on the transmission rate of an input signal to perform a phase synchronization control so that there is a fixed phase difference between the input signal and an oscillation output, whereby clock timing based on the transmission rate can be extracted. A regeneration control circuit sequentially sweeps a voltage threshold level and the phase of the extracted cock with respect to the input signal and determines whether the levels of adjacent monitor points match, whereby a decision point within the valid zone of the eye pattern can be automatically measured and used as the optimal point for regeneration control.

Abstract: A transmission apparatus has a main signal processing device, a monitor control part and an intermediating part to intermediate addresses and data between the monitor control part and the main signal processing device. The transmission apparatus further has a first switching part to selectively supply the address or the address and the data output from the intermediating part to the main signal processing device in the normal operation mode, and to selectively supply the address or the address and the data output from the monitor control part to the main signal processing device in the debug mode, and a second selecting part to selectively supply the data output from the intermediating part to the monitor control part in the normal operation mode, and to selectively supply the data output from the main signal processing device to the monitor control part in the debug mode.