Abstract: A luggage stowing device includes a second hand luggage detection unit detecting information of pieces of hand luggage transported by a main conveyor, a stowing robot stowing pieces of the hand luggage transported by the main conveyor with respect to two containers, and a stowing computation unit and a stowing control unit controlling the stowing robot such that at least one of the order of priority of the containers for stowing pieces of the hand luggage and the order of stowing pieces of the hand luggage in the containers with respect to the order of transporting pieces of the hand luggage is adjusted on the basis of the information of pieces of the hand luggage detected by the second hand luggage detection unit.

Abstract: An upper member of a steel piston has a chemical composition which consists of, in mass %, C: 0.15 to 0.30%, Si: 0.02 to 1.00%, Mn: 0.20 to 0.80%, P: 0.020% or less, S: 0.028% or less, Cr: 0.80 to 1.50%, Mo: 0.08 to 0.40%, V: 0.10 to 0.40%, Al: 0.005 to 0.060%, N: 0.0150% or less, O: 0.0030% or less, and the balance: Fe and impurities, and satisfies Formula (1) and Formula (2), in which, at a cross section parallel to the axial direction of the upper member, the number of Mn sulfides is 100.0 per mm2 or less, the number of coarse Mn sulfides having an equivalent circular diameter of 3.0 ?m or more is within a range of 1.0 to 10.0 per mm2, and the number of oxides is 15.0 per mm2 or less. 0.42?Mo+3V?1.50??(1) V/Mo?0.

Abstract: An upper member of a steel piston has a chemical composition which consists of, in mass %, C: 0.15 to 0.30%, Si: 0.02 to 1.00%, Mn: 0.20 to 0.80%, P: 0.020% or less, S: 0.028% or less, Cr: 0.80 to 1.50%, Mo: 0.08 to 0.40%, V: 0.10 to 0.40%, Al: 0.005 to 0.060%, N: 0.0150% or less, O: 0.0030% or less, and the balance: Fe and impurities, and satisfies Formula (1) and Formula (2), in which, at a cross section parallel to the axial direction of the upper member, the number of Mn sulfides is 100.0 per mm2 or less, the number of coarse Mn sulfides having an equivalent circular diameter of 3.0 ?m or more is within a range of 1.0 to 10.0 per mm2, and the number of oxides is 15.0 per mm2 or less. 0.42?Mo+3V?1.50??(1) V/Mo?0.

Abstract: A producing method of direct reduced iron includes the steps of: drying an oxidized iron raw material selected from a group including iron ore and iron-making dust generated in an iron-making process to have a predetermined moisture content; mixing the oxidized iron raw material subjected to the drying step and a reducing material having a predetermined moisture content to obtain a mixture; pulverizing the mixture obtained in the mixing step for 80% minus-sieve to have a particle diameter of 70 ?m to 500 ?m; kneading the mixture after the moisture content of the mixture subjected to the pulverizing step is adjusted; agglomerating the mixture subjected to the kneading step to be agglomerate; and reducing the agglomerate obtained in the agglomerating step by a rotary hearth furnace to generate direct reduced iron.

Abstract: A producing method of direct reduced iron includes the steps of: drying an oxidized iron raw material selected from a group including iron ore and iron-making dust generated in an iron-making process to have a predetermined moisture content; mixing the oxidized iron raw material subjected to the drying step and a reducing material having a predetermined moisture content to obtain a mixture; pulverizing the mixture obtained in the mixing step for 80% minus-sieve to have a particle diameter of 70 ?m to 500 ?m; kneading the mixture after the moisture content of the mixture subjected to the pulverizing step is adjusted; agglomerating the mixture subjected to the kneading step to be agglomerate; and reducing the agglomerate obtained in the agglomerating step by a rotary hearth furnace to generate direct reduced iron.

Abstract: A power-source controller for reducing current consumption while a DRAM is in standby, includes a mode detection circuit inverting a disable signal having an L-level under the enable state and having an H-level under the disable state; an internal-power-source driver circuit having first and second transistors; and an internal-power-source reference circuit setting first and second driver control signals respectively to L-level and H-level when an L-level disable signal is input to turn on the first transistor and turn off the second transistor, supplying an external-power-source voltage as an internal-power-source voltage, setting the first driver control signal to H-level when an H-level disable signal is input, controlling the level of the second driver control signal to turn off the second transistor and control the first transistor, and supplying an internal power-source voltage lower than the external-power-source voltage.

Abstract: To provide a power-source controller for reducing the current consumption while a DRAM is standby. The power-source controller is constituted by a mode detection circuit 4 for inverting an L-level disable signal under the enable state and inverting a disable signal into H-level under the disable state, an internal-power-source driver circuit 6 having Pch-Tr 6a and Pch-Tr 6b, and an internal-power-source reference circuit 5 for setting a first driver control signal to L-level and a second driver control signal to H-level when an L-level disable signal is input to turn on Pch-Tr 6b and turn off Pch-Tr 6a, supplying an external-power-source voltage VCC as an internal-power-source voltage IVC, setting a first driver control signal to H-level when an H-level disable signal is input, controlling the level of a second driver control signal to turn off Pch-Tr 6b and control Pch-Tr 6a, and supplying an internal power-source voltage IVC1 lower than the external-power-source voltage VCC.

Abstract: A low power consumption type dynamic random access memory (DRAM) operable with reduced current consumption responsive to an external signal, without causing occurrence of malfunction during low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits, while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to an externally provided power supply control signal, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.

Abstract: There provides a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside and without causing occurrence of malfunction at times of low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to a power supply control signal CONT inputted from outside, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.

Abstract: There provides a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside and without causing occurrence of malfunction at times of low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to a power supply control signal CONT inputted from outside, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.

Abstract: There provides a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside and without causing occurrence of malfunction at times of low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to a power supply control signal CONT inputted from outside, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.