Abstract: An IF filter band-limits an intermediate frequency signal outputted from a mixer. An AFC unit controls the oscillation frequency of a PLL so that the frequency of the intermediate frequency signal is a predetermined frequency. When the AFC unit controls the oscillation frequency of the PLL, a band control unit controls the passing characteristic of the IF filter to the passing characteristic of a wide band, and after the completion of the control, controls the passing characteristic of the IF filter to the passing characteristic of a narrow band. A frequency correction unit refers to a filter information storage unit, and corrects the oscillation frequency controlled by the AFC unit according to the difference between the center frequency of the passband of the passing characteristic of the wide band and the center frequency of the passband of the passing characteristic of the narrow band.

Abstract: An IF filter band-limits an intermediate frequency signal outputted from a mixer. An AFC unit controls the oscillation frequency of a PLL so that the frequency of the intermediate frequency signal is a predetermined frequency. When the AFC unit controls the oscillation frequency of the PLL, a band control unit controls the passing characteristic of the IF filter to the passing characteristic of a wide band, and after the completion of the control, controls the passing characteristic of the IF filter to the passing characteristic of a narrow band. A frequency correction unit refers to a filter information storage unit, and corrects the oscillation frequency controlled by the AFC unit according to the difference between the center frequency of the passband of the passing characteristic of the wide band and the center frequency of the passband of the passing characteristic of the narrow band.

Abstract: Degradation of a reception performance by an image signal is reduced. A semiconductor device includes: an oscillation circuit configured to generate a local signal; a mixer configured to multiply a reception signal by the local signal; an analog filter configured to filter a signal output from the mixer; an AD converter configured to digitalize a signal that has passed through the analog filter to generate a first signal; a digital filter configured to filter a signal that has passed through the AD converter to generate a second signal; a power comparator configured to detect the power difference between the first signal and the second signal; a register configured to store a theoretical power difference; and a determination unit configured to determine a frequency of the local signal based on the power difference from the theoretical power difference.

Abstract: Degradation of a reception performance by an image signal is reduced. A semiconductor device includes: an oscillation circuit configured to generate a local signal; a mixer configured to multiply a reception signal by the local signal; an analog filter configured to filter a signal output from the mixer; an AD converter configured to digitalize a signal that has passed through the analog filter to generate a first signal; a digital filter configured to filter a signal that has passed through the AD converter to generate a second signal; a power comparator configured to detect the power difference between the first signal and the second signal; a register configured to store a theoretical power difference; and a determination unit configured to determine a frequency of the local signal based on the power difference from the theoretical power difference.

Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.

Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.

Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.

Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.