Abstract: A semiconductor chip transmits a request signal which requests notification of the setting state of a chip identifier to another semiconductor chip connected to one of the upstream and downstream, receives a response signal indicating the setting state of the chip identifier and the value of the chip identifier, as a response to the request signal, and performs a chip identifier setting process based on the response signal. When receiving a request signal from another semiconductor chip connected to the other of the upstream and downstream, the semiconductor chip transmits a response signal indicating the setting state of the chip identifier and the value of the chip identifier, as a response to the request signal.

Abstract: A memory control circuit is configured to take a priority for each transfer instruction into account but not the priority in a memory access unit, and thus processing of a high-priority transfer instruction received during a memory access needs to wait for a long time. The memory control apparatus divides the received transfer instruction into a memory access unit and, when the transfer instruction having a higher priority is received during the memory access, the memory access based on a low-priority transfer instruction is interrupted and starts the memory access based on the high-priority transfer instruction.

Abstract: By connecting, to a bus bridge according to a configuration of a bus system, a monitor circuit including an activation control circuit generating a counter activation signal from an input monitor activation signal, a counter circuit, activated by the counter activation signal, counting the transfer number using a signal of bridge transfer completion indicating an issuance of one transfer from a bus bridge, and outputting a count completion signal when the transfers of the same number as that stuck in the bus bridge indicated by the signal of the transfer number stuck in the bridge is issued when being activated, and a completion control circuit outputting a monitor completion signal upon receiving the count completion signal from the counter circuit, consistency of data may be guaranteed in any bus system without changing the configuration of the bus bridge based on the number of masters accessing the bus bridge.

Abstract: A semiconductor chip transmits a request signal which requests notification of the setting state of a chip identifier to another semiconductor chip connected to one of the upstream and downstream, receives a response signal indicating the setting state of the chip identifier and the value of the chip identifier, as a response to the request signal, and performs a chip identifier setting process based on the response signal. When receiving a request signal from another semiconductor chip connected to the other of the upstream and downstream, the semiconductor chip transmits a response signal indicating the setting state of the chip identifier and the value of the chip identifier, as a response to the request signal.

Abstract: Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode.

Abstract: A memory access control device for controlling access to a plurality of memory devices with differing latency, controls, when performing a first access and then a second access, the timing of performing the second access, according to a memory device accessed in the first access and a memory device accessed in the second access.

Abstract: A memory control circuit is configured to take a priority for each transfer instruction into account but not the priority in a memory access unit, and thus processing of a high-priority transfer instruction received during a memory access needs to wait for a long time. The memory control apparatus divides the received transfer instruction into a memory access unit and, when the transfer instruction having a higher priority is received during the memory access, the memory access based on a low-priority transfer instruction is interrupted and starts the memory access based on the high-priority transfer instruction.

Abstract: A memory access control device for controlling access to a plurality of memory devices with differing latency, controls, when performing a first access and then a second access, the timing of performing the second access, according to a memory device accessed in the first access and a memory device accessed in the second access.

Abstract: A memory access control device for controlling access to a plurality of memory devices with differing latency, controls, when performing a first access and then a second access, the timing of performing the second access, according to a memory device accessed in the first access and a memory device accessed in the second access.

Abstract: An information processing system for performing processing of dividing a moving image into tiles and packetizing and outputting information corresponding to each tile includes a process time measuring packet generation unit adapted to generate and transmit a process time measuring packet in which a packet sending time is set to measure a packet process time, a packet process time measuring unit adapted to measure, based on the packet sending time set in the process time measuring packet and the reception time of the process time measuring packet, the packet process time necessary for processing a packet, a determination unit adapted to determine, based on the packet process time, the timestamp of the moving image divided into the tiles, and a packetization unit adapted to execute processing of packetizing and outputting the timestamp and the information of the moving image divided into the tiles.

Abstract: By connecting, to a bus bridge according to a configuration of a bus system, a monitor circuit including an activation control circuit generating a counter activation signal from an input monitor activation signal, a counter circuit, activated by the counter activation signal, counting the transfer number using a signal of bridge transfer completion indicating an issuance of one transfer from a bus bridge, and outputting a count completion signal when the transfers of the same number as that stuck in the bus bridge indicated by the signal of the transfer number stuck in the bridge is issued when being activated, and a completion control circuit outputting a monitor completion signal upon receiving the count completion signal from the counter circuit, consistency of data may be guaranteed in any bus system without changing the configuration of the bus bridge based on the number of masters accessing the bus bridge.

Abstract: A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access held up to a predetermined stage of the command queue.

Abstract: Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode.

Abstract: A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access held up to a predetermined stage of the command queue.

Abstract: A memory controller includes a plurality of bus interfaces and a memory controller core configured to control a command and data issued from the plurality of bus interfaces and to write or read the command and the data into and from the memory. The memory controller core includes a command control unit configured to receive a plurality of commands issued from the plurality of bus interfaces and to reorder and store the plurality of commands and a write data control unit configured to receive a plurality of pieces of write data issued from the plurality of bus interfaces in a sequence that the command control unit receives the write commands and to output the write data based on the reordered result of the command control unit. Accordingly, latency can be minimized between the memory controller and the memory and downsizing of a circuit of the memory controller can be achieved.

Abstract: An information processing system for performing processing of dividing a moving image into tiles and packetizing and outputting information corresponding to each tile includes a process time measuring packet generation unit adapted to generate and transmit a process time measuring packet in which a packet sending time is set to measure a packet process time, a packet process time measuring unit adapted to measure, based on the packet sending time set in the process time measuring packet and the reception time of the process time measuring packet, the packet process time necessary for processing a packet, a determination unit adapted to determine, based on the packet process time, the timestamp of the moving image divided into the tiles, and a packetization unit adapted to execute processing of packetizing and outputting the timestamp and the information of the moving image divided into the tiles.

Abstract: A memory access control device for controlling access to a plurality of memory devices with differing latency, controls, when performing a first access and then a second access, the timing of performing the second access, according to a memory device accessed in the first access and a memory device accessed in the second access.