Patents by Inventor Wataru Odashima
Wataru Odashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9735907Abstract: A transmission device to multiplex in a first signal a plurality of second signals each having a low rate as compared with the first signal, the transmission device includes: a plurality of memories to store the plurality of second signals; a selector to select one of the second signals read from the plurality of memories; and a controller to control read timing to read the plurality of second signals from the plurality of memories and signal selection timing to select the one of the second signals by the selector so as to execute rearrangement processing of the plurality of second signals read from the plurality of memories in accordance with cross-connect setting information for the plurality of second signals and shift processing of the plurality of second signals read from the plurality of memories in accordance with multiplexing positions of the plurality of second signals for the first signal.Type: GrantFiled: October 22, 2015Date of Patent: August 15, 2017Assignee: FUJITSU LIMITEDInventors: Hiromichi Makishima, Hidetaka Kawahara, Yuji Obana, Kazumasa Mikami, Wataru Odashima, Shingo Hotta, Hiroyuki Kitajima
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Patent number: 9729261Abstract: A transmission apparatus includes: a first mapping unit configured to allocate a first frame that stores a client signal to an intermediate frame; a second mapping unit configured to allocate the intermediate frame to a second frame that has a higher bit rate than a bit rate of the first frame; and a rate controller configured to control a bit rate of the intermediate frame based on the bit rate of the first frame and the bit rate of the second frame.Type: GrantFiled: January 12, 2015Date of Patent: August 8, 2017Assignee: FUJITSU LIMITEDInventors: Wataru Odashima, Hayato Furukawa, Toru Katagiri
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Patent number: 9584307Abstract: A transmission apparatus includes: a plurality of logical lanes; a receiver configured to receive a signal including synchronization information of a frame; a distributor configured to divide data included in the received signal into frame elements and cause the plurality of logical lanes to store the data; and a transmitter configured to transmit the data stored in the logical lanes to lines corresponding to the logical lanes. When the data is stored in the plurality of logical lanes, the distributor groups the logical lanes into a plurality of groups and associates the frame elements with the synchronization information.Type: GrantFiled: January 12, 2015Date of Patent: February 28, 2017Assignee: FUJITSU LIMITEDInventors: Hayato Furukawa, Wataru Odashima, Shota Shinohara, Toru Katagiri
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Patent number: 9525509Abstract: A data transmission device where a low-speed signal transmission frame is included in time slots of a high-speed signal transmission frame and a number of the time slots to include the low-speed signal transmission frame is variable, wherein the time slots have respective time slot numbers, includes a storage unit storing signal data of the high-speed signal transmission frame corresponding to the number of the time slots based on a time slot number basis, wherein the signal data of the high-speed signal transmission frame are supplied on the time slot number basis; and a selection and output unit selecting and sequentially outputting the signal data on the time slot number basis, wherein the signal data have been stored in accordance with the number of the time slots.Type: GrantFiled: March 1, 2013Date of Patent: December 20, 2016Assignee: FUJITSU LIMITEDInventors: Hidetaka Kawahara, Junichi Sugiyama, Wataru Odashima, Shota Shinohara, Hiroyuki Homma
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Publication number: 20160142798Abstract: A transmission apparatus includes: a reception processing unit configured to perform a reception processing on a first signal into which second signals having different rates and including overhead information are hierarchically multiplexed; and a common overhead processing unit configured to process the overhead information included in the first and second signals according to a common rate to hierarchical layers.Type: ApplicationFiled: October 21, 2015Publication date: May 19, 2016Applicant: FUJITSU LIMITEDInventors: HIDETAKA KAWAHARA, Hiromichi Makishima, Hiroyuki Kitajima, Yuji OBANA, Shingo HOTTA, Wataru Odashima
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Publication number: 20160142799Abstract: A transmission device to multiplex in a first signal a plurality of second signals each having a low rate as compared with the first signal, the transmission device includes: a plurality of memories to store the plurality of second signals; a selector to select one of the second signals read from the plurality of memories; and a controller to control read timing to read the plurality of second signals from the plurality of memories and signal selection timing to select the one of the second signals by the selector so as to execute rearrangement processing of the plurality of second signals read from the plurality of memories in accordance with cross-connect setting information for the plurality of second signals and shift processing of the plurality of second signals read from the plurality of memories in accordance with multiplexing positions of the plurality of second signals for the first signal.Type: ApplicationFiled: October 22, 2015Publication date: May 19, 2016Applicant: FUJITSU LIMITEDInventors: Hiromichi MAKISHIMA, Hidetaka KAWAHARA, Yuji OBANA, Kazumasa MIKAMI, Wataru ODASHIMA, Shingo HOTTA, Hiroyuki KITAJIMA
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Patent number: 9167320Abstract: A transmission method for transmitting a lower-speed signal transmission frame using a node device in a network by accommodating the lower-speed signal transmission frame into time slots of a higher-speed signal transmission frame includes supplying, when a number of the time slots accommodating the lower-speed signal transmission frame is to be increased, the time slots to input numbers of a cross-connection part of the node device in accordance with an order of time slot numbers of the time slots; and re-establishing cross-connections where the input numbers are cross-connected to corresponding output numbers of the cross-connection part so that the cross-connections are prevented from crossing each other, wherein the input numbers input the time slots and the output numbers output the time slots.Type: GrantFiled: March 20, 2013Date of Patent: October 20, 2015Assignee: FUJITSU LIMITEDInventors: Shota Shinohara, Wataru Odashima, Hiroyuki Homma, Junichi Sugiyama
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Publication number: 20150132012Abstract: A transmission apparatus includes: a plurality of logical lanes; a receiver configured to receive a signal including synchronization information of a frame; a distributor configured to divide data included in the received signal into frame elements and cause the plurality of logical lanes to store the data; and a transmitter configured to transmit the data stored in the logical lanes to lines corresponding to the logical lanes. When the data is stored in the plurality of logical lanes, the distributor groups the logical lanes into a plurality of groups and associates the frame elements with the synchronization information.Type: ApplicationFiled: January 12, 2015Publication date: May 14, 2015Inventors: Hayato Furukawa, Wataru Odashima, Shota Shinohara, Toru Katagiri
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Publication number: 20150125148Abstract: A transmission apparatus includes: a first mapping unit configured to allocate a first frame that stores a client signal to an intermediate frame; a second mapping unit configured to allocate the intermediate frame to a second frame that has a higher bit rate than a bit rate of the first frame; and a rate controller configured to control a bit rate of the intermediate frame based on the bit rate of the first frame and the bit rate of the second frame.Type: ApplicationFiled: January 12, 2015Publication date: May 7, 2015Inventors: Wataru Odashima, Hayato Furukawa, Toru Katagiri
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Patent number: 8891667Abstract: A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation.Type: GrantFiled: March 7, 2013Date of Patent: November 18, 2014Assignee: Fujitsu LimitedInventors: Junichi Sugiyama, Makoto Shimizu, Wataru Odashima, Shota Shinohara, Hiroyuki Homma
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Publication number: 20130259476Abstract: A transmission method for transmitting a lower-speed signal transmission frame using a node device in a network by accommodating the lower-speed signal transmission frame into time slots of a higher-speed signal transmission frame includes supplying, when a number of the time slots accommodating the lower-speed signal transmission frame is to be increased, the time slots to input numbers of a cross-connection part of the node device in accordance with an order of time slot numbers of the time slots; and re-establishing cross-connections where the input numbers are cross-connected to corresponding output numbers of the cross-connection part so that the cross-connections are prevented from crossing each other, wherein the input numbers input the time slots and the output numbers output the time slots.Type: ApplicationFiled: March 20, 2013Publication date: October 3, 2013Applicant: FUJITSU LIMITEDInventors: Shota SHINOHARA, Wataru Odashima, Hiroyuki Homma, Junichi Sugiyama
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Publication number: 20130259484Abstract: A data transmission device where a low-speed signal transmission frame is included in time slots of a high-speed signal transmission frame and a number of the time slots to include the low-speed signal transmission frame is variable, wherein the time slots have respective time slot numbers, includes a storage unit storing signal data of the high-speed signal transmission frame corresponding to the number of the time slots based on a time slot number basis, wherein the signal data of the high-speed signal transmission frame are supplied on the time slot number basis; and a selection and output unit selecting and sequentially outputting the signal data on the time slot number basis, wherein the signal data have been stored in accordance with the number of the time slots.Type: ApplicationFiled: March 1, 2013Publication date: October 3, 2013Applicant: FUJITSU LIMITEDInventors: Hidetaka KAWAHARA, Junichi SUGIYAMA, Wataru ODASHIMA, Shota SHINOHARA, Hiroyuki HOMMA
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Publication number: 20130243114Abstract: A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation.Type: ApplicationFiled: March 7, 2013Publication date: September 19, 2013Applicant: FUJITSU LIMITEDInventors: Junichi SUGIYAMA, Makoto SHIMIZU, Wataru ODASHIMA, Shota SHINOHARA, Hiroyuki HOMMA
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Publication number: 20060215710Abstract: In a frame communication method and device which can accurately reproduce received frames without being influenced by fluctuations of a frame interval caused by inter-channel multiplexing on a transmitting side, a frame interval is detected from transmission frames; information of the frame interval is added to the transmission frames; the transmission frames are multiplexed and transmitted. Also, the information of the frame interval is extracted from received frames demultiplexed; and the received frames are spaced by the frame interval to be transferred. When the frame interval exceeds a maximum frame interval determined by a bit number of the information of the frame interval, only information of the maximum frame interval is transmitted and information of subsequent remaining frame intervals is added to the transmission frames to be transmitted.Type: ApplicationFiled: July 27, 2005Publication date: September 28, 2006Inventors: Wataru Odashima, Katsuya Tsushita, Susumu Suwa, Yutaka Kosuge, Takayuki Kato, Takanobu Uegaki, Kenichi Kamada