Patents by Inventor Wataru Ootsuka

Wataru Ootsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9048423
    Abstract: A memory storage device including a lower electrode formed to be separate for each of a plurality of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer. The memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer. The memory storage layer and the upper electrode are formed in common to plural memory cells.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 2, 2015
    Assignee: SONY CORPORATION
    Inventor: Wataru Ootsuka
  • Publication number: 20140361237
    Abstract: A memory storage device including: a lower electrode formed to be separate for each of a plurality of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.
    Type: Application
    Filed: August 26, 2014
    Publication date: December 11, 2014
    Inventor: Wataru Ootsuka
  • Patent number: 8847189
    Abstract: A memory storage device including: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 30, 2014
    Assignee: Sony Corporation
    Inventor: Wataru Ootsuka
  • Publication number: 20140024196
    Abstract: A memory storage device including: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: Sony Corporation
    Inventor: Wataru Ootsuka
  • Patent number: 7372718
    Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: May 13, 2008
    Assignee: Sony Corporation
    Inventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
  • Patent number: 7239542
    Abstract: The present invention provides a storage apparatus including a variable resistance element having a recording layer between two electrodes. In the variable resistance element, a resistance value of the recording layer is reversibly changed to one of a value in a high-resistance state and a value in a low-resistance state by applying potentials of different polarities to the two electrodes. An absolute value of a threshold value of an applied signal at a time of change from the high-resistance state to the low-resistance state and an absolute value of a threshold value of an applied signal at a time of change from the low-resistance state to the high-resistance state differ from each other. A reading signal for detecting the resistance value of the recording layer in the variable resistance element is applied with a polarity of one of the threshold values of the applied signals which one has a higher absolute value and with a value lower than the absolute value.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: July 3, 2007
    Assignee: Sony Corporation
    Inventors: Wataru Ootsuka, Tomohito Tsushima, Hidenari Hachino
  • Publication number: 20060109316
    Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
    Type: Application
    Filed: October 4, 2005
    Publication date: May 25, 2006
    Inventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
  • Publication number: 20060092685
    Abstract: The present invention provides a storage apparatus including a variable resistance element having a recording layer between two electrodes. In the variable resistance element, a resistance value of the recording layer is reversibly changed to one of a value in a high-resistance state and a value in a low-resistance state by applying potentials of different polarities to the two electrodes. An absolute value of a threshold value of an applied signal at a time of change from the high-resistance state to the low-resistance state and an absolute value of a threshold value of an applied signal at a time of change from the low-resistance state to the high-resistance state differ from each other. A reading signal for detecting the resistance value of the recording layer in the variable resistance element is applied with a polarity of one of the threshold values of the applied signals which one has a higher absolute value and with a value lower than the absolute value.
    Type: Application
    Filed: October 5, 2005
    Publication date: May 4, 2006
    Inventors: Wataru Ootsuka, Tomohito Tsushima, Hidenari Hachino