Patents by Inventor Wataru Ootsuka
Wataru Ootsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9048423Abstract: A memory storage device including a lower electrode formed to be separate for each of a plurality of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer. The memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer. The memory storage layer and the upper electrode are formed in common to plural memory cells.Type: GrantFiled: August 26, 2014Date of Patent: June 2, 2015Assignee: SONY CORPORATIONInventor: Wataru Ootsuka
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Publication number: 20140361237Abstract: A memory storage device including: a lower electrode formed to be separate for each of a plurality of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.Type: ApplicationFiled: August 26, 2014Publication date: December 11, 2014Inventor: Wataru Ootsuka
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Patent number: 8847189Abstract: A memory storage device including: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.Type: GrantFiled: September 24, 2013Date of Patent: September 30, 2014Assignee: Sony CorporationInventor: Wataru Ootsuka
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Publication number: 20140024196Abstract: A memory storage device including: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.Type: ApplicationFiled: September 24, 2013Publication date: January 23, 2014Applicant: Sony CorporationInventor: Wataru Ootsuka
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Patent number: 7372718Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.Type: GrantFiled: October 4, 2005Date of Patent: May 13, 2008Assignee: Sony CorporationInventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
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Patent number: 7239542Abstract: The present invention provides a storage apparatus including a variable resistance element having a recording layer between two electrodes. In the variable resistance element, a resistance value of the recording layer is reversibly changed to one of a value in a high-resistance state and a value in a low-resistance state by applying potentials of different polarities to the two electrodes. An absolute value of a threshold value of an applied signal at a time of change from the high-resistance state to the low-resistance state and an absolute value of a threshold value of an applied signal at a time of change from the low-resistance state to the high-resistance state differ from each other. A reading signal for detecting the resistance value of the recording layer in the variable resistance element is applied with a polarity of one of the threshold values of the applied signals which one has a higher absolute value and with a value lower than the absolute value.Type: GrantFiled: October 5, 2005Date of Patent: July 3, 2007Assignee: Sony CorporationInventors: Wataru Ootsuka, Tomohito Tsushima, Hidenari Hachino
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Publication number: 20060109316Abstract: A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.Type: ApplicationFiled: October 4, 2005Publication date: May 25, 2006Inventors: Hajime Nagao, Hidenari Hachino, Tsutomu Sagara, Hironobu Mori, Nobumichi Okazaki, Wataru Ootsuka, Tomohito Tsushima, Chieko Nakashima
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Publication number: 20060092685Abstract: The present invention provides a storage apparatus including a variable resistance element having a recording layer between two electrodes. In the variable resistance element, a resistance value of the recording layer is reversibly changed to one of a value in a high-resistance state and a value in a low-resistance state by applying potentials of different polarities to the two electrodes. An absolute value of a threshold value of an applied signal at a time of change from the high-resistance state to the low-resistance state and an absolute value of a threshold value of an applied signal at a time of change from the low-resistance state to the high-resistance state differ from each other. A reading signal for detecting the resistance value of the recording layer in the variable resistance element is applied with a polarity of one of the threshold values of the applied signals which one has a higher absolute value and with a value lower than the absolute value.Type: ApplicationFiled: October 5, 2005Publication date: May 4, 2006Inventors: Wataru Ootsuka, Tomohito Tsushima, Hidenari Hachino