Abstract: A memory storage device includes: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.

Abstract: A memory device includes: a transistor array having transistors; and memory elements provided, one for each of the transistors. The transistor array includes a substrate having diffusion layers on a surface thereof, parallel word lines on the substrate, parallel first bit lines provided in a direction perpendicular to the word lines, bit contact electrodes between the adjacent two word lines and connecting the first bit lines and the diffusion layers, and node contact electrodes at an opposite side to the bit contact electrodes with the two word lines in between and connected to the diffusion layers. The memory elements have lower electrodes connected to the node contact electrodes, memory layers on the lower electrodes and having resistance values reversibly changing by voltage application, and parallel second bit lines extending in the same direction as that of the first bit lines on the memory layers.

Abstract: A resistance change memory device includes: memory cells each having a current path in which a storage element, whose resistance changes according to the voltage applied, and an access transistor are connected in series; first wirings each connected to one end of the current path; second wirings each connected to the other end of the current path; a well which is a semiconductor region in which the access transistors are formed; and a drive circuit.

Abstract: A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.

Abstract: A memory device includes: a transistor array having transistors; and memory elements provided, one for each of the transistors. The transistor array includes a substrate having diffusion layers on a surface thereof, parallel word lines on the substrate, parallel first bit lines provided in a direction perpendicular to the word lines, bit contact electrodes between the adjacent two word lines and connecting the first bit lines and the diffusion layers, and node contact electrodes at an opposite side to the bit contact electrodes with the two word lines in between and connected to the diffusion layers. The memory elements have lower electrodes connected to the node contact electrodes, memory layers on the lower electrodes and having resistance values reversibly changing by voltage application, and parallel second bit lines extending in the same direction as that of the first bit lines on the memory layers.

Abstract: A variable resistance memory device includes: a first common line; a second common line; plural memory cells each formed by serially connecting a memory element, resistance of which changes according to applied voltage, and an access transistor between the second common line and the first common line; a common line pass transistor connected between the first common line and a supply node for predetermined voltage; and a driving circuit that controls voltage of the second common line, the predetermined voltage, and voltage of a control node of the common line pass transistor and drives the memory cells.

Abstract: A memory storage device includes: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.

Abstract: A semiconductor memory device includes: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line. The sense amplifier circuit includes a differential sense amplifier, a pull-up section, a read gate transistor, and a threshold correction section.

Abstract: A resistance change memory device includes: memory cells each having a current path in which a storage element, whose resistance changes according to the voltage applied, and an access transistor are connected in series; first wirings each connected to one end of the current path; second wirings each connected to the other end of the current path; a well which is a semiconductor region in which the access transistors are formed; and a drive circuit.

Abstract: A variable resistance memory device includes: a first common line; a second common line; plural memory cells each formed by serially connecting a memory element, resistance of which changes according to applied voltage, and an access transistor between the second common line and the first common line; a common line pass transistor connected between the first common line and a supply node for predetermined voltage; and a driving circuit that controls voltage of the second common line, the predetermined voltage, and voltage of a control node of the common line pass transistor and drives the memory cells.

Abstract: One or serially connected field effect transistors are cross coupled with each other, first terminals of nonvolatile variable resistance elements are connected to their storage nodes, and the other terminals of the variable resistance elements are connected to a power supply line to thereby form a memory cell. By controlling the voltage supplied to this power supply line, data of the memory cell immediately before turning off the power is stored in it when the power is turned off.

Abstract: It is intended to provide a storage element having an arrangement which becomes able to be manufactured easily with high density. A storage element includes resistance changing elements 10 having recording layers 2, 3 provided between two electrodes 1, 4 and in which resistance values of the recording layers 2, 3 are reversibly changed with application of electric potential with different polarities to these two electrodes 1, 4, at least part of the layers 2, 3 constructing the recording layers of the resistance changing elements 10 being formed commonly by the same layer in a plurality of adjacent memory cells.

Abstract: A semiconductor memory device includes: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line. The sense amplifier circuit includes a differential sense amplifier, a pull-up section, a read gate transistor, and a threshold correction section.

Abstract: It is intended to provide a storage element having an arrangement which becomes able to be manufactured easily with high density. A storage element includes resistance changing elements 10 having recording layers 2, 3 provided between two electrodes 1, 4 and in which resistance values of the recording layers 2, 3 are reversibly changed with application of electric potential with different polarities to these two electrodes 1, 4, at least part of the layers 2, 3 constructing the recording layers of the resistance changing elements 10 being formed commonly by the same layer in a plurality of adjacent memory cells.

Abstract: A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.

Abstract: One or serially connected field effect transistors are cross coupled with each other, first terminals of nonvolatile variable resistance elements are connected to their storage nodes, and the other terminals of the variable resistance elements are connected to a power supply line to thereby form a memory cell. By controlling the voltage supplied to this power supply line, data of the memory cell immediately before turning off the power is stored in it when the power is turned off.

Abstract: A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.