Abstract: An input buffer of a semiconductor device is provided. A first voltage shift circuit converts an input signal formed of a low amplitude logic signal overlapping 1.65V or 2.9V to a first signal formed of a complimentary signal formed of the low amplitude logic signal overlapping 2.9V or 1.65V. A second voltage shift circuit converts a reference potential of 1.65V or 2.9V to a second signal of 2.9V or 1.65V. A differential amplifier compares the reference potential with the input signal when the reference potential is 1.65V, and compares the first signal and the second signal when the reference potential is 2.9V. The input buffer thus operates normally whichever of 1.65V and 2.9V is the reference potential.

Abstract: A lead-containing complex oxide containing substantially no alkali metal is produced under hydrothermal conditions in the absence of alkali metals using a Pb source which serves also as a mineralizer for precipitating the lead-containing complex oxide. Preferred Pb source acting as the mineralizer is lead oxide.

Abstract: In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.

Abstract: One strobe signal (QS) is outputted from a group of two adjacent memory chips (MC(i-1), MCi) in each module. In each group, the second memory chip (MCi) receives a data mask signal (DQM(i-1)) inputted to the adjacent first memory chip (MC(i-1)) as a data mask control signal (DQMCi), and stops outputting the strobe signal (QS) when both the data mask signal (DQMi) for the second memory chip (MCi) and the data mask control signal (DQMCi) are activated. Each memory chip (MCi) receives the data mask signal (DQMi) and stops outputting data. In a synchronous DRAM using a strobe signal as a trigger, this configuration allows reduction in the number of strobe signals.

Abstract: A power-on detecting circuit includes a capacitance for sensing power-on, and a signal generating circuit which responds to the output node potential of capacitance by generating a signal indicative of the power-on. The signal generating circuit includes inverter circuits forming a latch circuit. The power-on detecting circuit includes a control circuit, which adjusts driving capabilities of inverter circuits at the power-on and power-off, or an activation control circuit, which delays the activation timing. The control circuit differentiates the driving capability of the latch circuit formed of inverter circuits at the power-on from that at the power-off. Activation control circuit activates signal generating circuit at the time the potential of the output node ND10 of a sensing circuit rises above the potential of the output node of signal generating circuit.

Abstract: A circuit of a structure in which one end of a serial connection circuit of two capacitors is grounded, and the potential of another end is switched in a constant cycle is disclosed as a voltage generating circuit applicable to a half Vcc generating circuit, a substrate bias circuit, or the like. Electrical connection between a connection point between the capacitors and a predetermined load and electrical connection between the connection point and ground are controlled so that the potential of the connection point attains to be a constant potential in accordance with the ratio between the capacitance of the two capacitors in response to switching of the potential of the "another end" to a predetermined potential. As a result, a half Vcc generating circuit with reduced power consumption and layout area and a substrate bias circuit capable of biasing a semiconductor substrate to an arbitrary potential are realized.