Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

Abstract: A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

Abstract: The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region.

Abstract: The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region.

Abstract: A semiconductor device includes a semiconductor chip including a first circuit and a wiring substrate over which the semiconductor chip is mounted. The wiring substrate includes input signal wires transmitting an input signal to the semiconductor chip, output signal wires transmitting an output signal from the semiconductor chip, and first conductor planes supplied with a reference potential. When a wire cross-sectional area is defined as the cross-sectional area of each wire in a direction orthogonal to a direction in which the wire extends, the wire cross-sectional area of each input signal wire is smaller than the wire cross-sectional area of each output signal wire. In the thickness direction of the wiring substrate, each input signal wire is interposed between second conductor planes and third conductor planes each supplied with the reference potential. Between the output signal wires and the input signal wires, the third conductor planes are disposed.

Abstract: A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled.

Abstract: A semiconductor device includes a semiconductor chip including a first circuit and a wiring substrate over which the semiconductor chip is mounted. The wiring substrate includes input signal wires transmitting an input signal to the semiconductor chip, output signal wires transmitting an output signal from the semiconductor chip, and first conductor planes supplied with a reference potential. When a wire cross-sectional area is defined as the cross-sectional area of each wire in a direction orthogonal to a direction in which the wire extends, the wire cross-sectional area of each input signal wire is smaller than the wire cross-sectional area of each output signal wire. In the thickness direction of the wiring substrate, each input signal wire is interposed between second conductor planes and third conductor planes each supplied with the reference potential. Between the output signal wires and the input signal wires, the third conductor planes are disposed.

Abstract: A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled.

Abstract: A semiconductor device according to an embodiment has a first semiconductor component and a second semiconductor component which are electrically connected with each other via an interposer. The interposer has a plurality of first signal wiring paths, and a plurality of second signal wiring paths each having a path distance smaller than each of the plurality of first signal wiring paths. Furthermore, the first semiconductor component includes a first electrode, a second electrode, and a third electrode arranged in order in a first direction. Furthermore, the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode arranged in order in the first direction. Furthermore, the first electrode is connected with the fourth electrode via the first signal wiring path, the second electrode is connected with the fifth electrode via the first signal wiring path, and the third electrode is connected with the sixth electrode via the first signal wiring path.

Abstract: To provide an inexpensive semiconductor device capable of suppressing the influence by crosstalk. A semiconductor device includes a signal wiring disposed in an organic interposer, an output circuit which is coupled to a first end of the signal wiring and which sets an impedance so as to generate a reflected wave antiphase to a waveform transmitted to the first end and periodically outputs data, and an input circuit which is coupled to a second end of the signal wiring and sets an impedance so as to generate a reflected wave of the same phase as a waveform transmitted to the second end. An average delay of the signal wiring is set to be 1/integer of 2 or more relative to a half of a cycle of the data. A difference between the maximum and minimum values of a delay of a signal at each of other signal wirings disposed in the organic interposer is set to be not greater than the average delay.

Abstract: To provide an inexpensive semiconductor device capable of suppressing the influence by crosstalk. A semiconductor device includes a signal wiring disposed in an organic interposer, an output circuit which is coupled to a first end of the signal wiring and which sets an impedance so as to generate a reflected wave antiphase to a waveform transmitted to the first end and periodically outputs data, and an input circuit which is coupled to a second end of the signal wiring and sets an impedance so as to generate a reflected wave of the same phase as a waveform transmitted to the second end. An average delay of the signal wiring is set to be 1/integer of 2 or more relative to a half of a cycle of the data. A difference between the maximum and minimum values of a delay of a signal at each of other signal wirings disposed in the organic interposer is set to be not greater than the average delay.

Abstract: A semiconductor device according to an embodiment has a first semiconductor component and a second semiconductor component which are electrically connected with each other via an interposer. The interposer has a plurality of first signal wiring paths, and a plurality of second signal wiring paths each having a path distance smaller than each of the plurality of first signal wiring paths. Furthermore, the first semiconductor component includes a first electrode, a second electrode, and a third electrode arranged in order in a first direction. Furthermore, the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode arranged in order in the first direction. Furthermore, the first electrode is connected with the fourth electrode via the first signal wiring path, the second electrode is connected with the fifth electrode via the first signal wiring path, and the third electrode is connected with the sixth electrode via the first signal wiring path.

Abstract: To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.

Abstract: To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.

Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and a fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.

Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and a fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.

Abstract: A semiconductor device in which warpage is less likely to occur. In the semiconductor device, two semiconductor chips are mounted over a diagonal of a substrate and one of the semiconductor chips lies over the intersection of the two diagonals of the substrate. The semiconductor device gives a solution to the following problem. In order to implement a semiconductor device with a plurality of semiconductor chips mounted on a substrate, generally the substrate must have a larger area. If the area of the substrate is increased without an increase in its thickness, warpage or deformation of the semiconductor device is more likely to occur. It is difficult or impossible to mount a warped or deformed semiconductor device over a wiring substrate.

Abstract: A semiconductor device in which warpage is less likely to occur. In the semiconductor device, two semiconductor chips are mounted over a diagonal of a substrate and one of the semiconductor chips lies over the intersection of the two diagonals of the substrate. The semiconductor device gives a solution to the following problem. In order to implement a semiconductor device with a plurality of semiconductor chips mounted on a substrate, generally the substrate must have a larger area. If the area of the substrate is increased without an increase in its thickness, warpage or deformation of the semiconductor device is more likely to occur. It is difficult or impossible to mount a warped or deformed semiconductor device over a wiring substrate.