Patents by Inventor Wataru Tsukada
Wataru Tsukada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10199363Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.Type: GrantFiled: May 19, 2017Date of Patent: February 5, 2019Assignee: Micron Technology, Inc.Inventors: Wataru Tsukada, Masayuki Honda, Yoshihisa Fukushima, Scott Richard Cyr
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Publication number: 20170256527Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.Type: ApplicationFiled: May 19, 2017Publication date: September 7, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Wataru Tsukada, Masayuki Honda, Yoshihisa Fukushima, Scott Richard Cyr
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Patent number: 9691744Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.Type: GrantFiled: August 28, 2015Date of Patent: June 27, 2017Assignee: Micron Technology, Inc.Inventors: Wataru Tsukada, Masayuki Honda, Yoshihisa Fukushima, Scott Richard Cyr
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Patent number: 9478262Abstract: Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers.Type: GrantFiled: May 29, 2015Date of Patent: October 25, 2016Assignee: Micron Technology, Inc.Inventors: Wataru Tsukada, Takenori Sato
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Publication number: 20160064366Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.Type: ApplicationFiled: August 28, 2015Publication date: March 3, 2016Inventors: Wataru Tsukada, Masayuki Honda, Yoshihisa Fukushima, Scott Richard Cyr
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Publication number: 20160049180Abstract: Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers.Type: ApplicationFiled: May 29, 2015Publication date: February 18, 2016Inventors: WATARU TSUKADA, TAKENORI SATO
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Patent number: 8510629Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.Type: GrantFiled: October 20, 2010Date of Patent: August 13, 2013Assignee: Elpida Memory, Inc.Inventors: Wataru Tsukada, Shiro Harashima, Yoji Nishio
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Patent number: 8462535Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.Type: GrantFiled: July 16, 2012Date of Patent: June 11, 2013Assignee: Elpida Memory, Inc.Inventors: Shiro Harashima, Wataru Tsukada
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Publication number: 20130010514Abstract: Disclosed herein is a semiconductor module that includes a module substrate and a plurality of semiconductor devices mounted on the module substrate. Among the semiconductor devices, two of the semiconductor devices adjacent in a first direction differ in a mounting direction by 180°. Among the semiconductor devices, two of the semiconductor devices adjacent in a second direction perpendicular to the first direction differing in a mounting direction by 180°.Type: ApplicationFiled: July 2, 2012Publication date: January 10, 2013Inventor: Wataru TSUKADA
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Publication number: 20120281348Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Applicant: Elpida Memory, Inc.Inventors: Shiro Harashima, Wataru Tsukada
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Patent number: 8243488Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.Type: GrantFiled: October 11, 2011Date of Patent: August 14, 2012Assignee: Elpida Memory, Inc.Inventors: Shiro Harashima, Wataru Tsukada
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Publication number: 20120026772Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.Type: ApplicationFiled: October 11, 2011Publication date: February 2, 2012Applicant: Elpida Memory, Inc.Inventors: Shiro Harashima, Wataru Tsukada
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Patent number: 8054664Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.Type: GrantFiled: December 15, 2009Date of Patent: November 8, 2011Assignee: Elpida Memory, Inc.Inventors: Shiro Harashima, Wataru Tsukada
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Patent number: 8054643Abstract: A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other.Type: GrantFiled: January 30, 2009Date of Patent: November 8, 2011Assignee: Elpida Memory, Inc.Inventor: Wataru Tsukada
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Publication number: 20110093764Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.Type: ApplicationFiled: October 20, 2010Publication date: April 21, 2011Applicant: Elpida Memory, Inc.Inventors: Wataru TSUKADA, Shiro Harashima, Yoji Nishio
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Publication number: 20100157645Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.Type: ApplicationFiled: December 15, 2009Publication date: June 24, 2010Applicant: Elpida Memory, Inc.Inventors: Shiro Harashima, Wataru Tsukada
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Publication number: 20090236758Abstract: A semiconductor module has a plurality of semiconductor devices arranged on a substrate and mutually connected by signal bus wiring lines. Each pair of first semiconductor devices are connected to each other by the signal bus wiring lines, skipping a second semiconductor device located between the pair of first semiconductor devices.Type: ApplicationFiled: March 23, 2009Publication date: September 24, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Wataru Tsukada
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Publication number: 20090196009Abstract: A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other.Type: ApplicationFiled: January 30, 2009Publication date: August 6, 2009Applicant: Elpida Memory,Inc.Inventor: Wataru TSUKADA