Abstract: A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions.

Abstract: A field shield isolating structure forms a structure for isolating elements of a semiconductor device. The field shield isolating structure includes a field shield gate insulating film and field shield electrode formed on the semiconductor substrate in separate processes to constitute a quasi-MOS transistor using impurity regions of adjacent MOS transistors. The film thickness of the field shield gate insulating film is set arbitrarily, the threshold voltage of the quasi-MOS transistor is set high, and then elements are insulated and isolated, so that the transistor is operated in the off state. The upper surface of the field shield electrode is also covered with the upper insulating film. The thicknesses of the upper insulating film and of the field shield gate insulating film is adjusted to have such values that prevent turning ON of the MOS transistor by the capacitance divided voltage. The voltage may be applied from upper conductive layers such as word lines formed above the upper insulating film.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: A lower electrode of a stacked capacitor in accordance with the present invention is formed of a silicon layer formed by low pressure CVD method. The silicon layer is formed by thermal decomposition of monosilane gas at a prescribed temperature. By setting partial pressure of the monosilane gas and formation temperature at prescribed values, the silicon layer is formed to be in a transitional state between poly crystal and amorphous. Such silicon layer has large concaves and convexes on the surface thereof. Consequently, opposing areas of the electrodes of the capacitor can be increased, and therefore electrostatic capacitance of the capacitor is also increased.

Abstract: A semiconductor device according to the present invention comprises a substrate (4) in a periphery of which formed are elements isolating regions. A bonding pad (3) is formed above the elements isolating region with an isolation layer (7) provided therebetween. An underlying layer (12) having a buffering function is formed on a surface of the bonding pad and the semiconductor substrate. In case the elements isolating region is formed of LOCOS film (30), the underlying layer is formed between the bonding pad and the LOCOS film. In case the elements isolating region is of a field-shield structure (13, 14), the underlying layer (12) is formed by separating a part of a gate electrode layer (14) of the field shield into an island. The underlying layer buffers external force applied on the bonding pad in a bonding processing to prevent generation of cracks in the semiconductor layer.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: In a DRAM having stacked capacitor cells, elements are isolated by field shield isolating structure. The field shield isolating structure is formed surrounding both X and Y directions of the memory cell in the DRAM. The field shield isolating structure comprises an isolating electrode layer formed on a semiconductor substrate between adjacent memory cells with an insulating film interposed therebetween. Two impurity regions included in the adjacent memory cells and the isolating electrode layer constitute a MOS transistor. A voltage for maintaining the MOS transistor normally-off is applied to the isolating electrode layer. A portion of the stacked capacitor extends to the isolating electrode layer. One of the source/drain regions of the MOS transistor is formed in self-alignment, using a sidewall spacer formed of an insulating film on a sidewall of the field shield electrode as a mask.

Abstract: A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor had various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: Disclosed is an LDDMOSFET, in which a gate electrode (2) having a cross-sectional shape having a lower side and an upper side longer than the upper side is formed of only conductive materials, and diffusion layers (5b, 6b) of low concentration and high concentration constituting a drain are both formed so as to be overlapped with portions below the gate electrode (2) utilizing the shape of this gate electrode (2). Since the gate electrode (2) is formed of only the conductive materials, it becomes easy to word the gate electrode (2) so as to be in a desired shape. Since the diffusion layers (5b, 6b) of low concentration and high concentration constituting the drain are both overlapped with the portions below the gate electrode (2), the performance as a transistor is not degraded even if the polarity of the surface of the diffusion layer (5b, 6b) of low concentration is inverted by the effect of hot electrons.

Abstract: A semiconductor device comprises an MOSFET (13) comprising a switching gate electrode (5) and a field shield MOS structure (11) formed on an element isolating region of a semiconductor substrate (1) and performs the element isolation by applying a bias voltage to the field shield (9). The field shield (9) is provided on the element isolating region of the semiconductor substrate (1) through an insulating film (8). A sidewall spacer (12) having its width set such that the field shield (9) may be an offset gate is formed on the side portion of the field shield (9). Then, source and drain layers (6) are formed on the main surface of the semiconductor substrate (1) so as not to overlap with the field shield (9). According to the semiconductor device, since the field shield (9) is the offset gate, it is possible to set high the threshold value on a parasitic MOS transistor and miniaturize the elements.

Abstract: A DRAM having stacked capacitor cell comprises one transfer gate transistor and one capacitor. A thick insulating film having flat surface is formed on the surface of the transfer gate transistor and the like. A conductive film is formed on a surface of one impurity region of the transfer gate transistor. An opening portion deep enough to reach the conductive film is formed in the insulating film. The capacitor is formed in the opening portion and on the upper surface of the insulating film. A lower electrode of the capacitor is connected to the conductive film. An insulating film having a flat surface is formed by a reflow process employing thermal processing, plasma ECR CVD method and the like.

Abstract: A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.

Abstract: A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.

Abstract: A semiconductor device includes a substrate (4) in a periphery of which are formed elements isolating regions. A bonding pad (3) is formed above the elements isolating region, with an isolation layer (7) provided therebetween. An underlying layer (12) having a buffering function is formed on a surface of the bonding pad and the semiconductor substrate. In one aspect of the invention, wherein the elements isolating region is formed of LOCOS film (30), the underlying layer is formed between the bonding pad and the LOCOS film. In another aspect of the invention, the elements isolating region is of a field-shield structure (13, 14), and the underlying layer (12) is formed by separating a part of a gate electrode layer (14) of the field shield into an island. The underlying layer buffers the structure against an external force that is applied on the bonding pad in a bonding processing, to thereby prevent generation of cracks in the semiconductor layer.

Abstract: A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. N-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: In an element forming region (10) of a semiconductor substrate (1), there are provided a gate electrode (2), sidewall insulating films (4), impurity diffusion regions (5a and 5b) of a lower concentration having their one ends are overlapped with the side sections of the gate electrode (2), and impurity diffusion regions (6a and 6b) of a higher concentration having their one ends are overlapped with the side sections of the sidewall insulating films (4). In an element isolation region (7) of the semiconductor substrate, there are formed an electrostatic screening electrode (31) for element isolation and an insulating film (30) substantially enclosing the electrostatic screening electrode. By employing the electrostatic screening electrode (31) for element isolation in the LDD MOS transistor, there is obtained a semiconductor device of high performance and reliability which is free from intrusion of impurities from the element isolation region.

Abstract: A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.

Abstract: A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15).