Patents by Inventor Wayland B. Holland
Wayland B. Holland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5705404Abstract: A semiconductor device and method of making same which includes a semiconductor substrate having a moat region with an ion implant in the moat region and a window in the substrate spaced from the moat region, electrically decoupled therefrom and having an ion implant therein in the form of a predetermined pattern. The moat region can contain one or more active and/or passive components therein. The method of fabrication comprises providing a semiconductor wafer, forming a moat region and an associated window region on the wafer, forming at least portions of electrical devices in the moat region by implanting ions therein, forming a predetermined non-electrical component pattern in the window by implanting ions in the window concurrently with the implanting of ions in the moat and completing fabrication of at least one electrical component in the moat region.Type: GrantFiled: September 13, 1996Date of Patent: January 6, 1998Assignee: Texas Instruments IncorporatedInventors: Catherine M. Huber, Debra J. Dolby, Wayland B. Holland
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Patent number: 5596528Abstract: The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.Type: GrantFiled: September 22, 1995Date of Patent: January 21, 1997Assignee: Texas Instruments IncorporatedInventors: Cetin Kaya, Wayland B. Holland, Rabah Mezenner
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Patent number: 5594258Abstract: A semiconductor device and method of making same which includes a semiconductor substrate having a moat region with an ion implant in the moat region and a window in the substrate spaced from the moat region, electrically decoupled therefrom and having an ion implant therein in the form of a predetermined pattern. The moat region can contain one or more active and/or passive components therein. The method of fabrication comprises providing a semiconductor wafer, forming a moat region and an associated window region on the wafer, forming at least portions of electrical devices in the moat region by implanting ions therein, forming a predetermined non-electrical component pattern in the window by implanting ions in the window concurrently with the implanting of ions in the moat and completing fabrication of at least one electrical component in the moat region.Type: GrantFiled: February 3, 1995Date of Patent: January 14, 1997Assignee: Texas Instruments IncorporatedInventors: Catherine M. Huber, Debra J. Dolby, Wayland B. Holland
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Patent number: 5526315Abstract: The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11) to a source voltage (Vs) having a higher potential than the control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.Type: GrantFiled: February 13, 1995Date of Patent: June 11, 1996Assignee: Texas Instruments IncorporatedInventors: Cetin Kaya, Wayland B. Holland, Rabah Mezenner
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Patent number: 5467306Abstract: The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.Type: GrantFiled: October 4, 1993Date of Patent: November 14, 1995Assignee: Texas Instruments IncorporatedInventors: Cetin Kaya, Wayland B. Holland, Rabah Mezenner
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Patent number: 5428578Abstract: The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11 ) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11 ) to a source voltage (Vs) having a higher potential than the, control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.Type: GrantFiled: August 12, 1993Date of Patent: June 27, 1995Assignee: Texas Instruments IncorporatedInventors: Cetin Kaya, Wayland B. Holland, Rabah Mezenner
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Patent number: 5403753Abstract: A semiconductor device and method of making same which includes a semiconductor substrate having a moat region with an ion implant in the moat region and a window in the substrate spaced from the moat region, electrically decoupled therefrom and having an ion implant therein in the form of a predetermined pattern. The moat region can contain one or more active and/or passive components therein. The method of fabrication comprises providing a semiconductor wafer, forming a moat region and an associated window region on the wafer, forming at least portions of electrical devices in the moat region by implanting ions therein, forming a predetermined non-electrical component pattern in the window by implanting ions in the window concurrently with the implanting of ions in the moat and completing fabrication of at least one electrical component in the moat region.Type: GrantFiled: July 15, 1993Date of Patent: April 4, 1995Assignee: Texas Instruments IncorporatedInventors: Catherine M. Huber, Debra J. Dolby, Wayland B. Holland
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Patent number: 5278458Abstract: One aspect of the present invention includes a circuit for detecting when an input voltage exceeds a predetermined threshold. The circuit for detecting includes an input for receiving the input voltage. Further, the circuit includes a plurality of switching devices, wherein each of the switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path. The plurality of switching devices includes three switching devices. The first switching device has a first terminal coupled to the input and a second terminal coupled to a first node. The second switching device has a first terminal coupled to the first node and a second terminal coupled to a second node. Finally, the third switching device has a first terminal coupled to the second node.Type: GrantFiled: December 13, 1991Date of Patent: January 11, 1994Assignee: Texas Instruments IncorporatedInventors: Wayland B. Holland, Gary L. Howe, John F. Schreck