Patents by Inventor Wayne A. Bather

Wayne A. Bather has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100270622
    Abstract: The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured to introduce strain in a channel region below the gate structure.
    Type: Application
    Filed: July 7, 2010
    Publication date: October 28, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahalingam NANDAKUMAR, Wayne A. BATHER, Narendra Singh MEHTA, Lahir Shaik ADAM
  • Patent number: 6812073
    Abstract: A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: November 2, 2004
    Assignee: Texas Instrument Incorporated
    Inventors: Haowen Bu, Amitabh Jain, Wayne A. Bather, Stephanie Watts Butler
  • Publication number: 20040110352
    Abstract: A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 10, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Haowen Bu, Amitabh Jain, Wayne A. Bather, Stephanie Watts Butler
  • Patent number: 6686283
    Abstract: A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: February 3, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Shawn T. Walsh, John E. Campbell, Somit Joshi, James B. Friedmann, Michael J. McGranaghan, Janice D. Makos, Arun Sivasothy, Troy A. Yocum, Jaideep Mavoori, Wayne A. Bather, Joe G. Tran, Ju-Ai Ruan, Michelle L. Hartsell, Gregory B. Shinn
  • Publication number: 20030129804
    Abstract: A method of forming a semiconductor device includes doping at least one region of an at least partially formed semiconductor device. The method further includes depositing at least one spacer layer outwardly from the at least one region of the at least partially formed semiconductor device. The at least one deposited spacer layer is formed in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the at least partially formed semiconductor device.
    Type: Application
    Filed: May 14, 2002
    Publication date: July 10, 2003
    Inventors: Manoj Mehrotra, Wayne A. Bather, Reji K. Koshy, Amitabh Jain, Mark S. Rodder, Rajesh B. Khamankar, Paul A. Tiner, Rick L. Wise, Darin K. Wedel