Abstract: Switch systems and method to configure switch systems are disclosed. A switch system includes a first leaf module and a first spine module. The first leaf module includes a plurality of internal ports and external ports. The first spine module includes a plurality of ports. A midplane is configured to couple each of the internal port of first leaf module to a port of a first spine module such that a subset of internal ports of the first leaf module are always coupled to a known subset of first spine module. Other switch systems and methods to configure switch systems are disclosed.

Abstract: System and method to configure switch systems are disclosed. A switch system includes leaf modules with internal ports and spine modules with ports. A midplane includes first layers closer to a first side, second layers closer to a second side and third layers between the first layers and the second layers. The midplane receives the leaf modules and the spine modules about both the first side and the second side. Conductors of the third layers couple internal ports of the leaf modules about one side to a port of spine modules about the other side. Conductors of the first layers couple internal ports of the leaf modules with ports of the spine modules about the first side. Conductors of the second layers couple internal ports of the leaf modules with ports of the spine modules about the second side.

Abstract: Switch systems and method to configure switch systems are disclosed. A switch system includes a first leaf module and a first spine module. The first leaf module includes a plurality of internal ports and external ports. The first spine module includes a plurality of ports. A midplane is configured couple each of the internal port of first leaf module to a port of a first spine module such that a subset of internal ports of the first leaf module are always coupled to a known subset of first spine module. Other switch systems and methods to configure switch systems are disclosed.

Abstract: A computer system performs memory to memory transfer, task scheduling and I/O request handling via a group of dedicated processors (e.g. a memory interface unit, an I/O unit, a data transfer unit, and a task control unit). The memory interface unit facilitates data interaction between the memory and the remainder of the system. The I/O unit is coupled to the memory interface unit and performs high level I/O job functions including I/O job scheduling, I/O job path selection, gathering of job statistics and device management. The data transfer unit is coupled to the memory interface unit and moves data between memory locations. The task control unit, coupled to the memory interface unit, allocates and deallocates events, maintains the status of tasks running on the system and schedules the execution of tasks. A hierarchical error reporting scheme is used by all of the processors.

Abstract: The present invention involves the use of multiple I/O processors (204) and (206), configured in parallel in an I/O system (104), to increase system performance as well as enhance system resiliency. Performance is increased by programming one of the multiple I/O processors with the added ability to allocate received I/O job requests among the active I/O processors including itself, thus allowing for parallel processing. The I/O system resiliency is enhanced by ensuring that any one of the I/O processors can assume the tasks of any other I/O processor which may fail. The I/O system described above employs a load balancing algorithm to evenly distribute the I/O job functions among the active I/O processors.

Abstract: An apparatus for preventing bus contention among a plurality of data sources is described which creates signals to be used to disable two of three data sources which share a common bus immediately prior to a bus access cycle. The circuit employs a negative edge triggered flip-flop. This flip-flop generates disable signals which are shifted in phase by 90.degree. with respect to the bus access clock signal. These signals are active one-quarter of a clock cycle before a new bus cycle begins. The early disable serves to clear the bus for access by substantially eliminating the possibility that a slowly responding disabled data source is still active while a quickly responding enabled data source has just become active. The early disabling of the data signals does not result in loss of data. When all data sources on the bus are turned off, a high signal simply goes higher and a low signal rises slowly.