Abstract: A high performance pipelined virtual first-in first-out stack structure having a data stack portion and a split control stack portion is described. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers.

Abstract: A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers.

Abstract: A maintenance exerciser makes requests of certain inoperative and malfunctioning storage memory bank portions of a large scale storage memory unit concurrently that normal system requestors do request of remaining, correctly functional, storage memory bank portions of such storage memory unit. All requests are collectively prioritized in a priority network which, save for the circuit of the present invention, will not advance to successive prioritizations until each currently prioritized request is positively acknowledged by the requested storage memory bank.