Patents by Inventor Wayne A. Nunn
Wayne A. Nunn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9837188Abstract: Various aspects of the present disclosure are directed toward methods and apparatus that include a lead frame with a fixed external pin pitch. A differential signal path is provided that is characterized by bond-pad pitch range, wire length and wire diameter. The differential signal path carries signals in a frequency range between 5 GHz and 16.1 GHz with less than about 25 dB differential return loss (DDRL). Further, the signals are processed at a signal-processing node that is electrically coupled to the differential signal path by using the differential signal path to carry signals in a frequency range between 5 GHz and about 16.1 GHz.Type: GrantFiled: March 14, 2013Date of Patent: December 5, 2017Assignee: NXP B.V.Inventors: Wayne A. Nunn, Joe E. Schulze, Jim R. Spehar
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Publication number: 20140080456Abstract: Users can reconnect with old friends by using their existing printed physical yearbook. Friends pages are accessed by downloading our mobile app on their smartphone or tablet. Users use our mobile app image scanner similar to the way a QR code is scanned but in our case there is nothing added to the detected senior portrait. It works using an image recognition API.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Inventors: Robert Wayne Nunn, JR., Sevak Samuel Zaribian
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Publication number: 20140009001Abstract: Various aspects of the present disclosure are directed toward methods and apparatus that include a lead frame with a fixed external pin pitch. A differential signal path is provided that is characterized by bond-pad pitch range, wire length and wire diameter. The differential signal path carries signals in a frequency range between 5 GHz and 16.1 GHz with less than about 25 dB differential return loss (DDRL). Further, the signals are processed at a signal-processing node that is electrically coupled to the differential signal path by using the differential signal path to carry signals in a frequency range between 5 GHz and about 16.1 GHz.Type: ApplicationFiled: March 14, 2013Publication date: January 9, 2014Applicant: NXP B.V.Inventors: Wayne A. Nunn, Joe E. Schulze, Jim R. Spehar
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Publication number: 20130268909Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.Type: ApplicationFiled: June 5, 2013Publication date: October 10, 2013Inventors: James Raymond SPEHAR, Christian PAQUET, Wayne A. NUNN, Dominicus Marinus ROOZEBOOM, Joseph SCHULZE, Fatha KHALSA
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Patent number: 8482114Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.Type: GrantFiled: April 9, 2010Date of Patent: July 9, 2013Assignee: NXP B.V.Inventors: James Raymond Spehar, Christian Paquet, Wayne A. Nunn, Dominicus M. Roozeboom, Joseph E. Schulze, Fatha Khalsa
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Patent number: 7911057Abstract: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate.Type: GrantFiled: November 29, 2006Date of Patent: March 22, 2011Assignee: NXP B.V.Inventor: Wayne Nunn
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Publication number: 20110057302Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.Type: ApplicationFiled: April 9, 2010Publication date: March 10, 2011Applicant: NXP B.VInventors: James Raymond Spehar, Christian Paquet, Wayne A. Nunn, Dominicus M. Roozeboom, Joseph E. Schulze, Fatha Khalsa
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Publication number: 20080315389Abstract: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate.Type: ApplicationFiled: November 29, 2006Publication date: December 25, 2008Applicant: NXP B.V.Inventor: Wayne Nunn
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Publication number: 20060125079Abstract: In an example embodiment, an integrated circuit (105) is placed in a package (100), the package having signal pad connections, power connections, and ground connections. A lower strip line (110) is bonded by coupling a first ground connection (110a) of the IC (105) to a first package substrate ground connection (110b). After bonding the lower strip line, a plurality of wires (125) is bonded by a plurality of signal pads (125a) on a device die (105) being coupled to signal pad connections (125b) on the package substrate (100), the plurality of signal pads (125a) being in proximity to the first ground connection (110a) and the plurality of wires (125) maintained at a first predetermined distance from the lower strip line (110).Type: ApplicationFiled: December 4, 2003Publication date: June 15, 2006Inventors: Chris Wyland, Wayne Nunn