Abstract: Various aspects of the present disclosure are directed toward methods and apparatus that include a lead frame with a fixed external pin pitch. A differential signal path is provided that is characterized by bond-pad pitch range, wire length and wire diameter. The differential signal path carries signals in a frequency range between 5 GHz and 16.1 GHz with less than about 25 dB differential return loss (DDRL). Further, the signals are processed at a signal-processing node that is electrically coupled to the differential signal path by using the differential signal path to carry signals in a frequency range between 5 GHz and about 16.1 GHz.

Abstract: Various aspects of the present disclosure are directed toward methods and apparatus that include a lead frame with a fixed external pin pitch. A differential signal path is provided that is characterized by bond-pad pitch range, wire length and wire diameter. The differential signal path carries signals in a frequency range between 5 GHz and 16.1 GHz with less than about 25 dB differential return loss (DDRL). Further, the signals are processed at a signal-processing node that is electrically coupled to the differential signal path by using the differential signal path to carry signals in a frequency range between 5 GHz and about 16.1 GHz.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.